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TMS320F28377D: SDFM Timing, Clock @10MHz and @20MHz

Part Number: TMS320F28377D
Other Parts Discussed in Thread: TIDA-01606, , AMC1306M05

Tool/software:

Hi,

We are working with a TMS320F28377D on a ControlCard that is populated on a TIDA-01606 Evaluation Board.
We now have issues with the SDFM module not giving us correct measurement values when having maximum clock rate of 20MHz.
With a clock rate of 10MHz the measurement values are ok.
The following pictures show the clock (CH1, yellow) and data (CH2, red) signals @10MHz and @20MHz (persistent mode) directly measured at the ControlCard connector.


Both timing look the same in respect of the signal quality while switching the clock from low to high (rising edge). To me both timing run at the limit when consulting timing constraints from the datasheet.
So to me there is no change in the important timing between 10MHz and 20MHz clock rate.

Is there any other criteria beside the timing that can lead to this behaviour?

PS: Input qualification is 3-sample for clock and data (as recommended). SDFM is running in mode 0

PS2: Strange to me is that SDFM module expects data to change on the falling edge of clock and strobes for data on the rising edge of the clock. But as far as I know the TI modulators (like AMC1306M05 for example) changes data on the rising edge of clock. Therefore one always need to invert clock signal with GPxINV feature (?)

Any input is highly appreciated.

Best regards,
Patrick


  • Hi Patrick,

    Thanks for your patience.

    As long as the clock and data are following the spec given in datasheet section "6.11.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option".

    About PS2,  we don't have a mode to strobe on falling edge. let me check that. will let you know soon.

    Regards,

    Hadi

  • Hi Hadi,

    There was a bug in the TIDA-01606 firmware where the the setting of the compare values for CMPC and CMPD have been wrong (compare values higher than period register) with a 10MHz SDFM Clock resulting in no Sync  situation that in fact resulted in correct measurement values.
    With a 20MHz clock the calculalted compare values have also been wrong but resulted in a too late Sync violating the fact that the first two SDFM filter results are invalid. So setting those compare values correct results in valid measurement also with a 20MHZ SDFM clock.

    Long story short: The signal timing (and quality) of the 20MHz clock has never been the root cause of the problem.

    Regards,
    Patrick