TMS320F28069M: Software Reset Not Working Properly on TMS320F28069 (Processor Fails to Restart)

Hi Andrew,

When the watchdog triggers XRSn it goes through the Boot Cycle and comes up back to application code based on the boot mode selected.
If the boot mode is set to flash while you have flash programmed then it will jump to code upon WD XRSn trigger.

In case of the debugger connected you would need to set the emulation boot mode to jump to  entry point as shown in the flowchart below


Thanks

The problem is not solved; it has become even worse. Let me describe it in more detail:

I am working with LAUNCHXL-F28069M and BOOSTXL-DRV8305EVM , using MotorWare 18. The JP1 and JP2 are not installed. When working under the debugger, I use the BOOT settings: ON, ON, ON. In this mode, everything works, and I can debug the program successfully.

After debugging, I switch to the Flash boot mode. The BOOT settings are: ON, ON, OFF. I power on the system, and the program starts running, which I can confirm by the blinking LED. However, I cannot control the motor. Communication over CAN works fine.

If I press the Reset button or perform a software reset, everything starts working correctly, including motor control. But right after powering on for the first time, motor control is not functional.

I would appreciate any advice on what might be causing this issue.  

Andrew.

PS: i have 3x LAUNCHXL-F28069M. are the same.

Can you put gpio toggles in the part of the code that does the motor control you would need to see what part of the code it encounters the issue that is resolved by doing a XRSn.

Thanks

LED control is in main_isr. CAN communication in main.

I'm not sure if my problem is related to the cmd file. Here is my cmd.

// FILE:    F28069M.cmd
//
// TITLE:   Linker Command File For F28069M + Flash28_API Device

MEMORY
{
PAGE 0 :   /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAML0_1     : origin = 0x008000, length = 0x000C00     /* on-chip RAM block L0 and L1 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

   //FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
   FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */   
   FLASHA_D      : origin = 0x3E8000, length = 0x00FF80     /* on-chip FLASH */
   //FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   //FLASHA_B    : origin = 0x3EC000, length = 0x007F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD590, length = 0x0006A0	 /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDC30, length = 0x000B50    /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FE780, length = 0x00008C    /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FE80C, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2_3     : origin = 0x008C00, length = 0x001400     /* on-chip RAM block L2 */
   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
   RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
   RAML8       : origin = 0x012000, length = 0x001800     /* on-chip RAM block L8. From 0x13800 to 0x14000 is reserved for InstaSPIN */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */

   ECANA         : origin = 0x006000, length = 0x000040     /* eCAN-A control and status registers */
   ECANA_LAM     : origin = 0x006040, length = 0x000040     /* eCAN-A local acceptance masks */
   ECANA_MOTS    : origin = 0x006080, length = 0x000040     /* eCAN-A message object time stamps */
   ECANA_MOTO    : origin = 0x0060C0, length = 0x000040     /* eCAN-A object time-out registers */
   ECANA_MBOX    : origin = 0x006100, length = 0x000100     /* eCAN-A mailboxes */

   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
}

SECTIONS
{
   /*Flash28_API: // Applicable only when API is not in BootROM
   {
      -lFlash2806x_API_wFPU_Library.lib(.econst)
      -lFlash2806x_API_wFPU_Library.lib(.text)
   }                   LOAD = FLASHF,
                       RUN = RAML4_5,
                       LOAD_START(_Flash28_API_LoadStart),
                       LOAD_END(_Flash28_API_LoadEnd),
                       RUN_START(_Flash28_API_RunStart),
                       PAGE = 0*/

   /* Allocate program areas: */
   .cinit              : > FLASHA_D,   PAGE = 0
   .pinit              : > FLASHA_D,   PAGE = 0
   .text               : > FLASHA_D,   PAGE = 0
   codestart           : > BEGIN,      PAGE = 0
   ramfuncs            :
   {
      -lFlash2806x_API_wFPU_Library.lib(.econst)
      -lFlash2806x_API_wFPU_Library.lib(.text)
   }
                        LOAD = FLASHE,
                        RUN = RAML0_1, /*RAML0_1*/
                        LOAD_START(_RamfuncsLoadStart),
                        LOAD_END(_RamfuncsLoadEnd),
                        RUN_START(_RamfuncsRunStart),
                        PAGE = 0

   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0,      PAGE = 1
   .ebss               : > RAML2_3,    PAGE = 1
   .esysmem            : > RAML2_3,    PAGE = 1

   /* Initalized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA_D,   PAGE = 0
   .switch             : > FLASHA_D,   PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA_D,   PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
   
   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
   DMARAML5	           : > RAML5,      PAGE = 1
   DMARAML6	           : > RAML6,      PAGE = 1
   DMARAML7	           : > RAML7,      PAGE = 1
   DMARAML8	           : > RAML8,      PAGE = 1   

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
   /* Uncomment the section below if calling the IQNasin() or IQasin()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables3
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

   }
   */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.  */
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT

   persistent_memory   : > FLASHH,   PAGE = 1
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Hi Andrew,

Andrew Buckin said:

LED control is in main_isr. CAN communication in main.

Andrew Buckin said:

can confirm by the blinking LED. However, I cannot control the motor. Communication over CAN works fine.

So where is your motor control code ? Is that not executing ?

Andrew Buckin said:

But right after powering on for the first time, motor control is not functional.

I cant tell anything from your CMD file

Thanks