Tool/software:
SYSCLK = 100 MHz
PLLSYSCLK = 20MHz (XTAL_OSC) * 10 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
LSPCLK = 25MHzBased on the above SYSCLK and a default low speed peripheral clock divider of 4
SCIHBAUD = 0x0SCILBAUD = 0x5D
Based on the arguments passed to
SCI_setConfig(AMPLE_SCI_BASE, DEVICE_LSPCLK_FREQ, 230400, (SCI_CONFIG_WLEN_8 |
SCI_CONFIG_STOP_ONE |
SCI_CONFIG_PAR_NONE));
where
DEVICE_LSPCLK_FREQ = 25MHz
Based on the output of the SCI, the LSPCLK seems to be 175MHz.
- We created a project that just initializes the clocks and GPIOs. In the loop in main we set and clear GPIO_7 with no delays and compare the timing with the debugger and without the debugger. They performed the same way.
- We used the macro DEVICE_DELAY_US to create a square wave with GPIO_7 and it worked as expected. Timing was very precise with 10 us. We also test this with and without the debugger.