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TMS320F280049: LSPCLK is 7 times faster than expected

Part Number: TMS320F280049

Tool/software:

I am working on a project using F280049PMS and we ran into some issues with the LSPCLK. 
This is a second iteration of the board but on the DSP side we did not make any significant hardware or software changes. On the hardware, I am using the same crystal (TSX-322520.0000MF20G-AC3) connected to X1 and X2. We have the DSP talking to a ESP using Uart (SCI) and what we have observed is somehow the DSP is doing a baud rate 7 times faster than what we expected. Another observation is when we are using the debugger, the Timing for the SCI module works as expected. It is just when using the board's clock that this happens.

SYSCLK = 100 MHz 

PLLSYSCLK = 20MHz (XTAL_OSC) * 10 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)

LSPCLK = 25MHz

Based on the above SYSCLK and a default low speed peripheral clock divider of 4

SCIHBAUD = 0x0

SCILBAUD = 0x5D

Based on the arguments passed to 

SCI_setConfig(AMPLE_SCI_BASE, DEVICE_LSPCLK_FREQ, 230400, (SCI_CONFIG_WLEN_8 |
                                              SCI_CONFIG_STOP_ONE |
                                              SCI_CONFIG_PAR_NONE));

where 

DEVICE_LSPCLK_FREQ = 25MHz

Based on the output of the SCI, the LSPCLK seems to be 175MHz. 

The ePWM is working at the correct speed. The same code is able to work correctly on the older revision of the board but hardware wise I am not very clear what can cause this issue, especially since the UART connection are directly pin to pin from DSP to ESP. 
Several debug process have been done below:
 
We ran the sysctl_ex2_xclkout_config.c with our own configuration and GPIO_16 frequency was 12.5MHz. I am not sure if this value makes total sense. I was expecting something around 100MHz.
We also ran other tests:
  1. We created a project that just initializes the clocks and GPIOs. In the loop in main we set and clear GPIO_7 with no delays and compare the timing with the debugger and without the debugger. They performed the same way.
  2. We used the macro DEVICE_DELAY_US to create a square wave with GPIO_7 and it worked as expected. Timing was very precise with 10 us. We also test this with and without the debugger.
We are able to work around the issue by putting a multiplier on the LSPCLK when we do SCI setup in the software but it doesn’t seem to be a good solution. 
  • Hi  ,

    XLCKOUT has few configurations like clock divider and clock source selection by default the divider is set to /8.

    So if its reading 12.5 then its really 100Mhz (12.5 *8) which seems to match your SYSCLK

    sysctl_ex2_xclkout_config.c

    I suggest you look the example more closely and check the configurations.

    Check the LSPCLK divider, if you have further questions on clock configurations that are SPI or any other module specific. Let me know I can ask for the relevant expert to assist you on that specific peripheral.

    Thanks

  • Hello Prarthan, I am the Software Engineer working with Sicheng. We didn't run the sysctl_ex2_xclkout_config example as is, we just configure GPIO_16 to output the System Clock with the configuration of our project.

    And all the peripherals and comms work as expected (PWM, SPI, Timers) but the SCI. And this same configuration works as expected including the SCI when using the debugger.

  • Hi Alberto,

    So If I understand correctly is you are saying- Everything works fine when debugger is connected and when you disconnect debugger and run standalone SCI is not working as expected ?

    What do you mean by SCI not working as expected ? Can you explain exactly what you are observing ? How is this related to SCI clock ?

    Thanks

  • Hello Prarthan, the SCI clock seems to be 7 times faster than when the debugger is connected. We probed the signals and they looks like proper UART signals but just with the wrong baud rate.

  • Did you check the LSPCLK divider ? Is it configured to be /4  in your code ?

    Can you explain how you got to the 175Mhz number from the SCI output ?

    Thanks.

  • In our code, I don't configure the the LSPCLK divider as the default is /4. And as I mentioned before it works when the debugger is connected. I can try to explicitly configure it. And we haven't been able to explain the 175Mhz and that's the reason we need your help. 

  • Hi Albeto,

    There is no difference in with or without debugger connected for clock configurations.

    Can you check if the XCLKOUT for PLLSYSCLK shows same frequency with or without debugger connected.

    Thanks