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TMS320F28P650DK: Application issues.

Reed
Expert 2110 points

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi Team,

Using TMS320F28P650DK9 for EIMF communication with FPGA,
It will cause the A5 and A10 ports of the ADC (it is currently uncertain whether other AD ports are affected) to output a maximum voltage of 70mV (the more EMIF communication data, the higher the voltage). The following is the external circuit and test data of our DSP. Please help analyze and reply.

In the voltage sampling circuit, after the front-end voltage reduction, the voltages before and after R447 are 776mv and 727mv respectively (yellow channel in the attached image). The UDC_AD port is the ADCA5 port of the DSP, and the external input is removed. When the input is 0V, the front-end of R447 is 0V, and the back-end (i.e. DSP_AD port) is about 70mv.
Send the R447 front-end voltage to ADCA3, and the voltage is normal. In addition, after we turned off EIMF and communicated with FPGA, the A5 voltage also returned to normal.
Please help analyze the above information, thank you!

  • 0
    TI__Mastermind 39920 points

    Hi Reed,

    This is caused by cross-talk from the aggressing digital channels.  Moreover, the input network of 10K/1000pF in the ADC pin presents high impedance which requires fairly high ACQPS (sampling time) that will exceed the register width that has a max value of 511 (see section 18.14.2 Choosing an Acquisition Window Duration in the Technical Reference Manual for reference).  Also validate that the chosen ACQPS matches the one that is calculated when setting up the SOC/Sampling time using SysConfig tool using the actual R and C of the ADC input.  Not having sufficient sample and hold time will result to ADC input signal not settling to the correct value.

    Regards,

    Joseph