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TMS320F280049C: Uniflash .txt file image verification error and load warning

Part Number: TMS320F280049C
Other Parts Discussed in Thread: UNIFLASH

Tool/software:

I would like help in fixing an error/warning  when attempting to verify/load a ".txt" file to a f280049 launchpad 

The .txt file is the obtained by enabling the C2000 Hex Utility in code composer studio and selecting the TI-TXT hex format 

I am using UniFlash version: 8.8.1.4983

The program was compiled using Code Composer Studio: Version: 12.8.1.00005 

Uniflash results

a) .TXT file

Verify Image console display
[11/18/2024, 7:22:52 AM] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[11/18/2024, 7:22:52 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[11/18/2024, 7:22:52 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[11/18/2024, 7:22:53 AM] [ERROR] C28xx_CPU1: File Loader: Verification failed: Memory map prevented reading 0x100000@Program

Load Image console display 

[11/18/2024, 7:50:27 AM] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[11/18/2024, 7:50:27 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[11/18/2024, 7:50:27 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[11/18/2024, 7:50:28 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[11/18/2024, 7:50:28 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[11/18/2024, 7:50:28 AM] [WARNING] C28xx_CPU1: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.
[11/18/2024, 7:50:28 AM] [SUCCESS] Program Load completed successfully.

b) .OUT file

The ".out" does not produce any warnings or errors as shown below

Verify Image console display results

[11/18/2024, 7:53:27 AM] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[11/18/2024, 7:53:27 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[11/18/2024, 7:53:27 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[11/18/2024, 7:53:31 AM] [SUCCESS] C28xx_CPU1: Program verification successful for C:/Users/dnyar/workspace_v12/F280049C_ThreePhase/CPU1_FLASH/F280049C_ThreePhase.out

Load Image console display results

[11/18/2024, 7:54:58 AM] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[11/18/2024, 7:54:58 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[11/18/2024, 7:54:58 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[11/18/2024, 7:54:58 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[11/18/2024, 7:54:59 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[11/18/2024, 7:54:59 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[11/18/2024, 7:54:59 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[11/18/2024, 7:55:11 AM] [SUCCESS] Program Load completed successfully.

Thanks

David Nyarko

  • Hello,

    What were the options used to generate the hex files?

    Thanks

    ki

  • The only options i have are included in the screenshots below. The other "C2000 Hex Utility" do not have any entries or checked options.

    Thanks

    David

  • I believe for C2000 you typically need to set memwidth and romwidth to 16. There may be some other options needed.

    I'll bring this thread to the attention of the C2000 experts.

  • Thanks

  • Hi David,

    Are you choosing to use ALIGN(8) when configuring the addresses in your linker cmd file before generating the project?

    Thanks and regards,

    Charles

  • Not sure where that should be. I have included my linker command file below:

    MEMORY
    {
    PAGE 0 :
       /* BEGIN is used for the "boot to Flash" bootloader mode   */
    
       BEGIN           	: origin = 0x080000, length = 0x000020
       RAMM0           	: origin = 0x0000F6, length = 0x00030A
    
       RAMLS0          	: origin = 0x008000, length = 0x000800
       RAMLS1          	: origin = 0x008800, length = 0x000800
       RAMLS2      		: origin = 0x009000, length = 0x000800
       RAMLS3      		: origin = 0x009800, length = 0x000800
       RAMLS4      		: origin = 0x00A000, length = 0x000800
       RESET           	: origin = 0x3FFFC0, length = 0x000002
    
       /* Flash sectors */
       /* BANK 0 */
       FLASH_BANK0_SEC0  : origin = 0x080020, length = 0x000FE0	/* on-chip Flash */
       FLASH_BANK0_SEC1  : origin = 0x081000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC2  : origin = 0x082000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC3  : origin = 0x083000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC4  : origin = 0x084000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC5  : origin = 0x085000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC6  : origin = 0x086000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC7  : origin = 0x087000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC8  : origin = 0x088000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC9  : origin = 0x089000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000	/* on-chip Flash */
    
       /* BANK 1 */
       FLASH_BANK1_SEC0  : origin = 0x090000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC1  : origin = 0x091000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC2  : origin = 0x092000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC3  : origin = 0x093000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC4  : origin = 0x094000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC5  : origin = 0x095000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC6  : origin = 0x096000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC7  : origin = 0x097000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC8  : origin = 0x098000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC9  : origin = 0x099000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000	/* on-chip Flash */
       FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0	/* on-chip Flash */
    
    //   FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010  /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
    PAGE 1 :
    
       BOOT_RSVD       : origin = 0x000002, length = 0x0000F1     /* Part of M0, BOOT rom will use this for stack */
       RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
    //   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
       RAMLS5      : origin = 0x00A800, length = 0x000800
       RAMLS6      : origin = 0x00B000, length = 0x000800
       RAMLS7      : origin = 0x00B800, length = 0x000800
    
       RAMGS0      : origin = 0x00C000, length = 0x002000
       RAMGS1      : origin = 0x00E000, length = 0x002000
       RAMGS2      : origin = 0x010000, length = 0x002000
       RAMGS3      : origin = 0x012000, length = 0x001FF8
    //   RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    }
    
    
    SECTIONS
    {
       codestart        : > BEGIN,     PAGE = 0, ALIGN(4)
       .text            : >> FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC5 | FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7 | FLASH_BANK0_SEC8 | FLASH_BANK0_SEC9 | FLASH_BANK0_SEC10,   PAGE = 0, ALIGN(4)
       .cinit           : > FLASH_BANK0_SEC1,     PAGE = 0, ALIGN(4)
       .switch          : > FLASH_BANK0_SEC1,     PAGE = 0, ALIGN(4)
       .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
    
       .stack           : > RAMM1,     PAGE = 1
    
    #if defined(__TI_EABI__)
       .init_array      : > FLASH_BANK0_SEC1,       PAGE = 0,       ALIGN(4)
       .bss             : > RAMLS5,       PAGE = 1
       .bss:output      : > RAMLS3,       PAGE = 0
       .bss:cio         : > RAMLS0,       PAGE = 0
       .data            : >> RAMLS5 | RAMLS6 | RAMLS7 | RAMGS0,       PAGE = 1
       .sysmem          : > RAMLS5,       PAGE = 1
       /* Initalized sections go in Flash */
       .const           : > FLASH_BANK0_SEC4,       PAGE = 0,       ALIGN(4)
    #else
       .pinit           : > FLASH_BANK0_SEC1,       PAGE = 0,       ALIGN(4)
       .ebss            : > RAMLS5,       PAGE = 1
       .esysmem         : > RAMLS5,       PAGE = 1
       .cio             : > RAMLS0,       PAGE = 0
       .econst          : > FLASH_BANK0_SEC4,    PAGE = 0, ALIGN(4)
    #endif
    
       ramgs0           : > RAMGS0,    PAGE = 1
       ramgs1           : > RAMGS1,    PAGE = 1
    
     
    #if defined(__TI_EABI__) 
       .TI.ramfunc      : LOAD = FLASH_BANK0_SEC1,
                          RUN = RAMLS0,
                          LOAD_START(RamfuncsLoadStart),
                          LOAD_SIZE(RamfuncsLoadSize),
                          LOAD_END(RamfuncsLoadEnd),
                          RUN_START(RamfuncsRunStart),
                          RUN_SIZE(RamfuncsRunSize),
                          RUN_END(RamfuncsRunEnd),
                          PAGE = 0, ALIGN(4)
    #else					  
       .TI.ramfunc      : LOAD = FLASH_BANK0_SEC1,
                          RUN = RAMLS0,
                          LOAD_START(_RamfuncsLoadStart),
                          LOAD_SIZE(_RamfuncsLoadSize),
                          LOAD_END(_RamfuncsLoadEnd),
                          RUN_START(_RamfuncsRunStart),
                          RUN_SIZE(_RamfuncsRunSize),
                          RUN_END(_RamfuncsRunEnd),
                          PAGE = 0, ALIGN(4)
    #endif
    
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    

    Thanks

    David

  • Hi David,

    Uniflash doesn't support the ti_txt file format. Please try using the hex format instead by leaving the output format dropdown blank in the C2000 Hex Utility. If this project is to be used with a flash kernel/sent over SCI, see the post build steps listed in Serial Flash Programming of C2000 Microcontrollers (Rev. H) section 3.

    Best,

    Alex

  • Hi Alex,

    The purpose of the .txt option is to be sent over SCI. Regarding the post build steps since the Section 3 of the document you referenced mentioned  the following:

    This file format can even be generated as part of the Code Composer Studio build process by adding a post-build step with the following options: "${CG_TOOL_HEX}" "${BuildArtifactFileName}" -boot -sci8 -a -o "${BuildArtifactFileBaseName}.txt"

    Where can i enter that in the CCS properties for my project.

    Thanks

    David Nyarko

  • David,

    There are two ways to enter those properties:

    • In the C2000 Hex Utility menus, tick the options/select the dropdowns that match those command options
    • Disable the C2000 Hex Utility, then paste the "${CG_TOOL_HEX}..." string onto a new line in the Build > Steps > Post-build steps box

    Best,

    Alex