Tool/software:
hi,
My customer is using F2808 in volume production. They use a boot code which is configuring PLL to operate at 50MHz - there are no issues with this configuration.
Their application re-configures the PLL to 100Mhz
In few of the boards, they see the code entering into illegal ISR, when the application configures the clock to 100MHz.
The R&D team, when they configure the application enable clock at 80Mhz, they see no issues.
Need help in debugging this issue further.
regards,
Frangline.
