• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 83 subscribers
  • Views 268 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28P650SH: CMPSS CBC goes wrong

chuanhui.weng
Prodigy 30 points
Part Number: TMS320F28P650SH
Other Parts Discussed in Thread: C2000WARE

Tool/software:

Hi  ,

    I encountered a problem when I used the CMPSS CBC to achieve the peak mode control buck.

    The PWM will be high at the start of the cycle and the current of inductance will rise, and the CMPSS will compare the ADC of current of inductance and the DAC value to produce a signal to shut down the PWM. In this way， I can  control the buck convertor.

    You can see the picture below:

CH1: ADC of current of inductance

CH3: Output Xbar of CMPSS CTRIPOUTL(CMPSS output)

CH4:DAC value(by DACA module)（Used to see the changing trend）

      You can see the current go up at the start of the cycle, and go down when the current equal to the DAC value。

     But see the  red box circled part,  the ouput Xbar sustained high when the current goes down(the DAC value didn't changed), and the current didn't goes up when the next cycle comes.

     Ask the TI's engineers what will cause the above problems, thanks

  • 0
    TI__Expert 7100 points

    Hello,

    Thanks for your patience.

    From this image it is obvious there are noise in the signals.

    Can you try to use the digital filter inside CMPSS module to remove the noise ? there is an example inside your C2000ware directory for configuring the digital filter.

    Regards,

    Hadi

  • 0 in reply to Hadi Moradisizkoohi
    Prodigy 30 points

    Hi Hadi，

           According to my recent use of CMPSS,  I found two problems with CMPSS:

          1. the first one is my question below,  I used the CMPSS ramp delay function，if the current sample matched the comparison value just at he moment when RAMP DELAY = 0, the comparator will assert until the next period start, and the EPWM TZ CBC will be latch in the next period. That's why the epwm output is low in the next period

         2. I found in the test that the RAMP DELAY's clock is systick instead of RAMPxCLK