Tool/software:
I want to execute the eCANA Rx ISR callback but with mailboxes configured for "no acceptance mask" for TMS320F28032 controller using device support library. I have configured respective CANLAM and CANGAM register as per datasheet but still unable to receive the data in particular configured mailbox meanwhile the ISR itself is not executing. Below is the code for reference:
//###########################################################################
//
// FILE: DSP2803x_ECan.c
//
// TITLE: DSP2803x Enhanced CAN Initialization & Support Functions.
//
//###########################################################################
//
// Included Files
//
#include "DSP2803x_Device.h" // DSP28 Headerfile Include File
#include "DSP2803x_Examples.h" // DSP28 Examples Include File
//
// InitECan - This function initializes the eCAN module to a known state.
//
void
InitECan(void)
{
InitECana();
}
//
// InitECana - Initialize eCAN-A module
//
void
InitECana(void)
{
//
// Create a shadow register structure for the CAN control registers.
// This is needed, since only 32-bit access is allowed to these registers.
// 16-bit access to these registers could potentially corrupt the register
// contents or return false data.
struct ECAN_REGS ECanaShadow;
//
// EALLOW enables access to protected bits
//
EALLOW;
//
// Configure eCAN RX and TX pins for CAN operation using eCAN regs
//
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
//
// Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
// HECC mode also enables time-stamping feature
//
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
//
// Initialize all bits of 'Message Control Register' to zero
// Some bits of MSGCTRL register come up in an unknown state.
// For proper operation, all bits (including reserved bits) of MSGCTRL must
// be initialized to zero
//
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
//
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
//
ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits
ECanaRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
//
// Configure bit timing parameters for eCANA
//
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
//
// Wait until the CPU has been granted permission to change
// the configuration registers
//
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set
ECanaShadow.CANBTC.all = 0;
//
// The following block is only for 60 MHz SYSCLKOUT.
// (30 MHz CAN module clock Bit rate = 125 Kbps)
// See Note at end of file.
//
ECanaShadow.CANBTC.bit.BRPREG = 15;
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
ECanaShadow.CANBTC.bit.TSEG1REG = 10;
ECanaShadow.CANBTC.bit.SAM = 0;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
//
// Wait until the CPU no longer has permission to change
// the configuration registers
//
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to clear
//
// Disable all Mailboxes
//
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.STM = 0; // Ensure self-test mode is off
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
EDIS;
}
//
// InitECanGpio - This function initializes GPIO pins to function as eCAN pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// Only one GPIO pin should be enabled for CANTXA operation.
// Only one GPIO pin shoudl be enabled for CANRXA operation.
// Comment out other unwanted lines.
//
void
InitECanGpio(void)
{
InitECanaGpio();
}
//
// InitECanaGpio - Configure eCAN-A module GPIO pins to function as eCAN pins
//
void
InitECanaGpio(void)
{
EALLOW;
//
// Enable internal pull-up for the selected CAN pins
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
//
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)
//
// Set qualification for selected CAN pins to asynch only
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
//
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
//
// Configure eCAN-A pins using GPIO regs
// This specifies which of the possible GPIO pins will be
// eCAN functional pins.
//
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 to CANRXA
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 to CANTXA
EDIS;
}
//
// Note: Bit timing parameters must be chosen based on the network parameters
// such as the sampling point desired and the propagation delay of the network.
// The propagation delay is a function of length of the cable, delay introduced
// by the transceivers and opto/galvanic-isolators (if any).
//
// The parameters used in this file must be changed taking into account the
// above mentioned factors in order to arrive at the bit-timing parameters
// suitable for a network.
//
//
// End of file
//
/*
* USER_PeripheralConfig.c
*
* Created on: 13-Nov-2024
* Author: PRPATIL
*/
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
extern __interrupt void canRxISR(void);
extern void USER_CPU_TimerConfig(void);
extern void USER_ECAN_A_Config(void);
void CONFIGURE_CAN_MAILBOX(Uint8 messageIdType, Uint32 messageId, int16 MBXnbr);
void INITIALIZE_ALL_MAILBOXES(void);
void USER_CPU_TimerConfig(void)
{
InitCpuTimers(); // For this example, only initialize the Cpu Timers
//
// Configure CPU-Timer 0 interrupt every second:
// 60MHz CPU Freq, 100ms Period (in uSeconds)
//
ConfigCpuTimer(&CpuTimer0, 60, 100000);
//
// To ensure precise timing, use write-only instructions to write to the
// entire register. Therefore, if any of the configuration bits are changed
// in ConfigCpuTimer and InitCpuTimers (in DSP2803x_CpuTimers.h), the
// below settings must also be updated.
//
CpuTimer0Regs.TCR.all = 0x4000; //write-only instruction to set TSS bit = 0
//
// Step 5. User specific code, enable interrupts:
//
//
// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
//
IER |= M_INT1;
//
// Enable TINT0 in the PIE: Group 1 interrupt 7
//
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
}
void USER_ECAN_A_Config(void)
{
struct ECAN_REGS ECanaShadow;
EALLOW;
InitECanaGpio();
InitECana(); // Initialize eCAN-A module
EALLOW;
ECanaRegs.CANMD.all = 0xFFFF0000;
ECanaRegs.CANGAM.all = 0xFFFFFFFF;
ECanaLAMRegs.LAM16.all = 0xFFFFFFFF;
ECanaLAMRegs.LAM17.all = 0xFFFFFFFF;
ECanaLAMRegs.LAM18.all = 0xFFFFFFFF;
INITIALIZE_ALL_MAILBOXES();
//TX Mailboxes
CONFIGURE_CAN_MAILBOX(1,0X12121212,0);
CONFIGURE_CAN_MAILBOX(1,0X13131313,1);
EALLOW;
ECanaRegs.CANME.all = 0xFFFFFFFF;
// Enable CAN interrupts
EALLOW;
ECanaRegs.CANMIL.all = 0xFFFF0000;
ECanaRegs.CANMIM.all = 0xFFFF0000; // Enable interrupts only for mailboxes 16-31
ECanaRegs.CANGIM.bit.I1EN = 1; // Enable Interrupt Line 1
EDIS;
}
void CONFIGURE_CAN_MAILBOX(Uint8 messageIdType, Uint32 messageId, int16 MBXnbr)
{
EALLOW;
volatile struct MBOX *Mailbox = &ECanaMboxes.MBOX0 + MBXnbr;
Mailbox->MSGID.all = 0;
if (messageIdType) //1: Extended CAN, 0:Standard CAN
{
Mailbox->MSGID.all = (messageId & 0x1FFFFFFF) | 0x80000000;
}
else
{
Mailbox->MSGID.all = (messageId & 0x7FF);
}
Mailbox->MSGCTRL.bit.DLC = 8;
Mailbox->MDL.all = 0x00000000;
Mailbox->MDH.all = 0x00000000;
EDIS;
}
void INITIALIZE_ALL_MAILBOXES(void)
{
EALLOW;
int32 i;
for(i = 0; i<=31;i++)
{
volatile struct MBOX *Mailbox = &ECanaMboxes.MBOX0 + i;
Mailbox->MSGID.all = 0;
Mailbox->MSGCTRL.bit.DLC = 8;
Mailbox->MDL.all = 0x00000000;
Mailbox->MDH.all = 0x00000000;
}
EDIS;
}
//###########################################################################
//
// FILE: main.c
//###########################################################################
//
// Included Files
//
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
//
// Prototype statements
//
void mailbox_read(int16 i);
//
// Globals
//
Uint32 ErrorCount;
Uint32 PassCount;
Uint32 MessageReceivedCount;
Uint32 TestMbox1 = 0;
Uint32 TestMbox2 = 0;
Uint32 TestMbox3 = 0;
Uint16 TestCounter = 0;
// Global variables for CAN message data
volatile Uint32 receivedID;
volatile Uint16 receivedData;
//TIMER
__interrupt void cpu_timer0_isr(void);
void USER_CPU_TimerConfig(void);
void USER_ECAN_A_Config(void);
//
// Exeternal defines d by the linker
//
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadSize;
extern Uint16 RamfuncsRunStart;
//
// Main
//
void main(void)
{
//Uint16 j;
//struct ECAN_REGS ECanaShadow;
InitSysCtrl();
InitECanGpio();
DINT;
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2803x_DefaultIsr.c.
// This function is found in DSP2803x_PieVect.c.
//
InitPieVectTable();
//
// Step 5. User specific code, enable interrupts:
//
EALLOW;
PieVectTable.TINT0 = &cpu_timer0_isr;
EDIS;
// Map CAN interrupt to the ISR
EALLOW;
//PieVectTable.ECAN1INTA = &canRxISR;
PieVectTable.ECAN1INTA = ECAN1INTA_ISR;
EDIS;
//Timer Configuration
USER_CPU_TimerConfig();
USER_ECAN_A_Config();
IER |= M_INT9;
PieCtrlRegs.PIEIER9.bit.INTx6 = 1; // Enable ECAN1INTA in PIE group 9
memcpy((Uint16 *)&RamfuncsRunStart,(Uint16 *)&RamfuncsLoadStart,
(unsigned long)&RamfuncsLoadSize);
//
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
//
InitFlash();
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
for(;;)
{
}
}
//
// cpu_timer0_isr - Timer0 counter
//
__interrupt void
cpu_timer0_isr(void)
{
CpuTimer0.InterruptCount++;
ECanaRegs.CANTRS.all = 0x00000003; //Set TRS for all transmit mailboxes
//
// Wait for TAn bits to be set
//
while(ECanaRegs.CANTA.all != 0x00000003 )
{
}
ECanaRegs.CANTA.all = 0x00000003; // Clear all TAn
MessageReceivedCount++;
//
// Acknowledge this interrupt to receive more interrupts from group 1
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
__interrupt void ECAN1INTA_ISR(void)
{
TestCounter++;
if (ECanaRegs.CANGIF1.bit.GMIF1 == 1)
{
Uint16 mailboxNumber = ECanaRegs.CANGIF1.bit.MIV1;
if (mailboxNumber >= 16 && mailboxNumber <= 31)
{
// Access the individual RMP bits (RMP16 - RMP31) based on mailboxNumber
switch(mailboxNumber)
{
case 16:
if (ECanaRegs.CANRMP.bit.RMP16) {
// Handle received message for mailbox 16
// Clear the RMP16 flag
mailbox_read(16);
ECanaRegs.CANRMP.bit.RMP16 = 1;
}
break;
case 17:
if (ECanaRegs.CANRMP.bit.RMP17) {
mailbox_read(17);
ECanaRegs.CANRMP.bit.RMP17 = 1;
}
break;
case 18:
if (ECanaRegs.CANRMP.bit.RMP18) {
mailbox_read(18);
ECanaRegs.CANRMP.bit.RMP18 = 1;
}
break;
case 19:
if (ECanaRegs.CANRMP.bit.RMP19) {
mailbox_read(19);
ECanaRegs.CANRMP.bit.RMP19 = 1;
}
break;
default:
break;
}
}
ECanaRegs.CANGIF1.bit.GMIF1 = 0; // Clear interrupt flag
}
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Clear PIE ACK
}
void mailbox_read(int16 MBXnbr)
{
volatile struct MBOX *Mailbox;
Mailbox = &ECanaMboxes.MBOX0 + MBXnbr;
TestMbox1 = Mailbox->MDL.all; // = 0x9555AAAn (n is the MBX number)
TestMbox2 = Mailbox->MDH.all; // = 0x89ABCDEF (a constant)
TestMbox3 = Mailbox->MSGID.all; // = 0x9555AAAn (n is the MBX number)
}
//
// End of File
//