• State TI Thinks Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 2 answers
  • Subscribers 84 subscribers
  • Views 475 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28377D: Timer priority between timer-0 and timer 1

SAGAR NENA
Prodigy 40 points
Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE

Tool/software:

Hi,

Timer 1 (INT13)is directly connected to the CPU.

Timer o (INT1) is connected via PIE Group.

So, I want to know between timer0 and timer1 which one having highest priority. 

  • 0
    TI__Mastermind 22470 points

    Hello,

    This expert is currently out of office due to holiday. Please expect a delay in response until after 12/3.

    Best Regards,

    Allison

  • 0
    TI__Genius 16545 points

    Hello,

    Interrupts of lower-numbered values are prioritized by the CPU, so the Timer 0 interrupt (from the ePIE) will have a higher priority than Timer 1. If you need to change these priorities, there is a C2000ware example that does interrupt nesting with the CPU timer interrupts: [C2000ware install]/driverlib/f2837xd/examples/cpu1/interrupt/interrupt_ex3_sw_prioritization.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 40 points

    Dear Delaney,

    Thank you for your response.

    However, I believe the information you provided applies only to interrupts connected via the PIE group. In this case, Timer 1 is directly connected to the CPU.

    I have verified using software that Timer 1 has a higher priority than Timer 0. To support this, I have attached a document for your reference. Please review the document and guide me further regarding the priority mechanism.

    Looking forward to your clarification.

  • 0 in reply to SAGAR NENA
    TI__Genius 16545 points

    Hi Sagar,

    Are you running the interrupt_ex3_sw_prioritization example I mentioned? It looks like the timer 1 ISR is being nested inside the timer 0 ISR, which is what the example configures with software prioritization. Without this software prioritization implemented, timer 0 would have top priority to finish executing before the timer 1 ISR is branched to. The example effectively swaps the prioritization order of all the CPU timer interrupts.

    At the CPU level, interrupts are prioritized numerically (the same way as the ePIE prioritizes within a group) with low-numbered interrupt groups having a higher priority (which includes the INT13 and INT14 groups). Each time the CPU is ready to execute another interrupt, it will go to the highest priority interrupt that is enabled.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 40 points

    HI Delaney,

    No i am not running interrupt_ex3_sw_prioritization example.

    Timer 1 is not nested inside the timer 0 isr.

    i used both timer individual.

  • 0 in reply to SAGAR NENA
    TI__Genius 16545 points

    Hi Sagar,

    Can you send your configuration code, and I will take a look? I will be out of office until 12/30 but can provide a response when I return. I apologize for any inconvenience.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 40 points

    Hi Delaney,

    Thank you for your quick response.

    here i have attached my software please look it over and let me know if you have any suggestions.

    Software.zip

  • 0
    TI__Genius 13445 points

    Hi,

    The expert is currently out of office until after the holidays. Please expect a delay in response. Thank you for your patience.

    Best Regards,

    Aishwarya

  • 0 in reply to Aishwarya Rajesh
    TI__Genius 16545 points

    Hi Sagar,

    It looks like the behavior you are seeing isn't due to the fact that Timer 1 has a higher priority than Timer 0, but rather that the Timer 1 interrupt is coming in first, and since there is no nesting enabled, it will run to completion even if an interrupt for Timer 0 comes in during the execution. By default, ISRs will complete execution before servicing the next interrupt that is both enabled and flagged. If you want Timer 0 to always be immediately serviced no matter what, you will have to enable nesting inside the Timer 1 interrupt. 

    A better way to test the priorities between the two Timer interrupts is also to set their periods and prescalers to the same values so that both interrupts are always triggered simultaneously. In this case, you should see that Timer 0 is always serviced first since it has a lower numerical interrupt number, and therefore higher priority in the ePIE.

    Best Regards,

    Delaney