hi all,
I am using a PWM to trigger my ADC ISR, when I toggle an output in the ADC ISR, The delay between each sampling is 400Khz. I need 800Khz at least.
has anyone an idea of what I am doing wrong to be so slow ???.
Thanks a million for your support,
greg.
void InitCan(void)
{
// Specific clock setting
SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/2*ADC_MODCLK
// init the ADC, calibration
InitAdc();
// ADC SETUP
//sequential sampling mode
AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0;
AdcRegs.ADCMAXCONV.all = 0x0000;
// Set up ADC to perform 1ere conversions on A0
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
// selection reference exterieure 2.048V
AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1;
//enable ISR to CPU
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;
AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;
//ADC operates as a 16-state sequencer
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1;
AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
}
interrupt void adc_isr(void)
{
GpioDataRegs.GPASET.bit.GPIO2 = 1;
g_AdcMesure.uiVoieMes[g_iCptMes] = AdcRegs.ADCRESULT0 >>4;
// Reinitialize for next ADC sequence
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
// Acknowledge interrupt to PIE
PieCtrlRegs.PIEACK.bit.ACK6 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO2 = 1;
}
void InitEPwm(void)
{
// Initialize ePWM2
//---------------------------------------------------------------------
//--- Must disable the clock to the ePWM modules if you
//--- want all ePMW modules synchronized.
//---------------------------------------------------------------------
asm(" EALLOW"); // Enable EALLOW protected register access
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
asm(" EDIS"); // Disable EALLOW protected register access
//---------------------------------------------------------------------
//--- Configure ePWM2 to trigger the ADC at 800 kHz rate
//---------------------------------------------------------------------
EPwm2Regs.TBCTL.bit.CTRMODE = 0x3; // Disable the timer
EPwm2Regs.TBCTL.all = 0xC033; // Configure timer control register
// bit 15-14 11: FREE/SOFT, 11 = ignore emulation suspend
// bit 13 0: PHSDIR, 0 = count down after sync event
// bit 12-10 000: CLKDIV, 000 => TBCLK = HSPCLK/1
// bit 9-7 000: HSPCLKDIV, 000 => HSPCLK = SYSCLKOUT/1
// bit 6 0: SWFSYNC, 0 = no software sync produced
// bit 5-4 11: SYNCOSEL, 11 = sync-out disabled
// bit 3 0: PRDLD, 0 = reload PRD on counter=0
// bit 2 0: PHSEN, 0 = phase control disabled
// bit 1-0 11: CTRMODE, 11 = timer stopped (disabled)
EPwm2Regs.TBCTR = 0x0000; // Clear timer counter
EPwm2Regs.TBPRD = ADC_SAMPLE_PERIOD; // // 187 = (187.5-1) = 150 MHz SYSCLKOUT / 800 KHz sampling
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Set timer phase
EPwm2Regs.ETPS.all = 0x0100; // Configure SOCA
// bit 15-14 00: EPWMxSOCB, read-only
// bit 13-12 00: SOCBPRD, don't care
// bit 11-10 00: EPWMxSOCA, read-only
// bit 9-8 01: SOCAPRD, 01 = generate SOCA on first event
// bit 7-4 0000: reserved
// bit 3-2 00: INTCNT, don't care
// bit 1-0 00: INTPRD, don't care
EPwm2Regs.ETSEL.all = 0x0A00; // Enable SOCA to ADC
// bit 15 0: SOCBEN, 0 = disable SOCB
// bit 14-12 000: SOCBSEL, don't care
// bit 11 1: SOCAEN, 1 = enable SOCA
// bit 10-8 010: SOCASEL, 010 = SOCA on PRD event
// bit 7-4 0000: reserved
// bit 3 0: INTEN, 0 = disable interrupt
// bit 2-0 000: INTSEL, don't care
EPwm2Regs.TBCTL.bit.CTRMODE = 0x0; // Enable the timer in count up mode
//---------------------------------------------------------------------
//--- Enable the clocks to the ePWM module.
//--- Note: this should be done after all ePWM modules are configured
//--- to ensure synchronization between the ePWM modules.
//---------------------------------------------------------------------
asm(" EALLOW"); // Enable EALLOW protected register access
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // HSPCLK to ePWM modules enabled
asm(" EDIS"); // Disable EALLOW protected register access
}