TMS320F280037: inquiry for implementation of ADC with DMA

Hi Robin,

Just to make sure I understand, are they trying to have a CPU timer trigger the DMA periodically to move the data from the ADCA and ADCB ADCRESULT0 -ADCRESULT15 registers into the last field of each element in the tADC structure (replacing the NULL's)? Some potential issues:

• Why is the destination address starting at tADC[eADC_Max] (shouldn't it be starting at the first element in the structure)? Also, what is eADC_Max equal to?
• Why is the transfer source step being used 29?
• Also keep in mind that one-shot mode enabled will mean only one trigger from the CPU timer module will move the entire transfer - so 6 16-bit values at a time.

I'm a little confused on how they want the data to be placed into their structure, please give an example of what they want moved over with each trigger.

Best Regards,

Delaney

Hi Delaney,

There is some mistake when I move the code to here. The destination address starting address is tADC[0].RawADCValue. Here are what I want.

First trigger -> Transfer0 ( Burst one shot(ADCAResults0 / ADCAResults1 / ADCAResults2 ) -> Transfer1 ( Burst one shot(ADCBResults0 / ADCBResults1 / ADCBResults2 )

Second trigger -> repeat

The expected results are

ADCAResults0 -> tADC[0].RawADCValue

ADCAResults1 -> tADC[1].RawADCValue

ADCAResults2 -> tADC[2].RawADCValue

ADCBResults0 -> tADC[3].RawADCValue

ADCBResults1 -> tADC[4].RawADCValue

ADCBResults2 -> tADC[5].RawADCValue

So, I set (size to 3 / step 1) for burst and for transfer source step to 29(ADCB_BASE - ADCA_BASE - 3).

And as I set in .TXT, one-shot is only for the burst Not transfer. I set as below.

DMA_configMode(DMA_CH1_BASE, DMA_TRIGGER_TINT0, (DMA_CFG_ONESHOT_ENABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT));

I am still working on it but cannot find what I miss. The current results are as below with my code.

ADCAResults0 -> tADC[0].RawADCValue // transfered

ADCAResults1 -> tADC[1].RawADCValue // transfered

ADCAResults2 -> tADC[2].RawADCValue // transfered

ADCBResults0 -> tADC[3].RawADCValue // transfered

ADCBResults1 -> tADC[4].RawADCValue // transfered

ADCBResults2 -> tADC[5].RawADCValue // Not transfer.

thanks,

Regards,

Hi Robin,

I apologize for the delay; I am looking into this and should have a response back to you by tomorrow.

Best Regards,

Delaney

Hi Robin,

I see, thank you for clarifying. Your settings look good for what you are trying to achieve, except for the 0 destination transfer step. I believe you want to change this to be sizeof(stADC) as well since this will be the number of addresses to increment between each burst. Please try this and see if it fixes the issue. If it doesn't, please view and send the status fields of the DMA CH1 CONTROL register after the trigger has taken place. It also appears that you want to use a wrap of some sort if you are trying to do multiple transfers and continuously store data inside the stADC structure (which I assume so if you have continuous mode enabled). 

Best Regards,

Delaney