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TMS320F28374S: After SysConfig setting still need to set TZCLR and TZOSTCLR

Julia Li
Expert 4455 points
Part Number: TMS320F28374S
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi Champs,

Customer wants to use GPIO27 as the TZ signal to Epwm12, the specific method is as follows:
GPIO27 as the input source for InputXbar4; As shown below:

Then configure EPWMXbar:

DCxEVT is used as the trigger signal for TZ

However, customer found that after they had configured it with sysconfig, they needed to set below registers, as follows:
EPwm1Regs.TZCLR.all = 0x7fff; EPwm1Regs.TZOSTCLR.all = 0x00ff;
Otherwise, EPwm1Regs.TZOSTFLG.bit.DCAEVT1 will be set to 1, is this a configuration issue? Or it do need to manually clear the TZCLR after using SysConfig.

Could you help to check this? Thanks!

Julia

  • 0
    TI__Mastermind 23550 points

    Hi Julia, 

    I will try to provide a response this week. Apologies for the delay and thanks for your patience!

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Expert 4455 points

    Hi Allison,

    Is there any updates? Thanks!

    Julia

  • +1 in reply to Julia Li
    TI__Mastermind 23550 points

    Hi Julia,

    Thank you kindly for your patience. To restate, the customer is trying to use GPIO27 as a one-shot trip to drive both EPWM channels (A and B) low? If this is the only requirement, they could actually do this without the digital compare submodule - just input XBAR straight to the EPWM as a one-shot trip source.

    • Right now, customer settings indicate the following path:
      • GPIO27 --> INPUT XBAR input4  --> EPWM XBAR --> TRIP4 --> DCxL --> DCAEVT1 event when DCxL is low --> One-Shot Trip forces EPWMxA/B low
    • My thought is they could simplify to:
      • GPIO27 --> INPUT XBAR input1 --> TRIP1 --> One-Shot Trip forces EPWMxA/B low

    If there is a specific reason they are using the digital compare submodule DCAEVT1 or you have doubts, please let me know.

    Regardless of the above, when the trip occurs (due to GPIO27), it will remain until manually cleared. For the DCAEVT1 case, when EPWM1 TZOSTFLG[DCAEVT1] reads a 1, this indicates a trip has occurred on the DCAEVT1 event, so the corresponding flag should be cleared manually. The TRM also clarifies that the OST flags must be manually cleared when it states the following:

    There is also this note to highlight in case it has been missed:

    From what you said in the original post, the customer is doing the following as a solution (which I don't think is necessary here)

    • EPwm1Regs.TZCLR.all = 0x7fff
      • Writing to TZCLR to clear ALL flags for event latches (interrupt, CBC, OST, DCxEVTy)
      • As well as set CTR = PRD pulse to clear the CBC trip latch.
    • EPwm1Regs.TZOSTCLR.all = 0x00ff
      • Writing to TZOSTCLR to clear ALL of the flags for the one-shot trip latch

    The only necessary flags to clear in the current customer case are those related to OST DCAEVT1 trip since that is the only event you are wanting to use. (another side note, I would also be careful writing to entire registers without masking for your specific register fields as there are reserved bits in some of these registers that can be mistakenly written to). Let me know if you have follow up questions.

    Best Regards,

    Allison