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Original question:

TMS320F2800137: Internal oscillators accuracy need to be less than 1%.(-30℃~90℃).

TMS320F2800137: External precision resistor issue (ExtR)

Albert Lu
Prodigy 70 points

Part Number: TMS320F2800137

Tool/software:

Hi experts,

I found CAN baud rate unstable problem in 2800137 MCU and ExtR solution can get stable CAN clock. I already do some testing by heating or cooling MCU to different temperature . The SYSCLK in abnormal MCU is from 121.7 to 121.4 MHz depend on high or low temperature but this MCU with ExtR solution will get more accuracy SYSCLK, from 120.0 to 120.3MHz.

Although ExtR solution can help us to get more accuracy SYSCLK but I found the RF signal is different under spectrum analyzer, see the following figure. ExtR solution will get more wide range dominant frequencies and

I afraid that will derived some EMI or EMS issue. Why is the ExtR solution changing dominant frequencies ? Is there any other potential risk?

 

The following figure is system clock without ExtR solution. System clock from MCU internal OSC2.

dominant frequencies of MCU with internal OSC2 clock

The following figure is system clock with ExtR solution. System clock from MCU external OSC2.

dominant frequencies of MCU with ExtR solution

Thanks

  • 0
    TI__Mastermind 41690 points

    Hi Albert,

    Sorry for the late response as this was automatically assigned in my inbox while i was out of office.  Anyway, i have a question regarding the spectrum plots.  For the non ExtR SYSCLK spectrum data (top plot), what was the source of the device clock?  Is it the internal oscillator or an external clock?  The top spectrum has a very narrow bandwidth but mean frequency is off by around 1MHz.  Just wanted to understand why it has narrow bandwidth compared to ExtR,

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Prodigy 70 points

    Hi Joseph

    Source clock of first figure is INTOSC2. 

    PLL setting is :

    >#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_OSC2 | SYSCTL_IMULT(48) | \
    >SYSCTL_REFDIV(1) | SYSCTL_ODIV(4) | \
    >SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
    >SYSCTL_DCC_BASE_0)

    Second figure PLL setting is: 

    >#define DEVICE_SETCLOCK_CFG_EXTR (SYSCTL_OSCSRC_EXTROSC2 | SYSCTL_IMULT(48) | \
    >SYSCTL_REFDIV(1) | SYSCTL_ODIV(4) | \
    >SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
    >SYSCTL_DCC_BASE_0)

    Should I modify my clock configure?

    thanks

  • 0 in reply to Albert Lu
    TI__Mastermind 41690 points

    Hi Albert,

    ExtR clock configuration is correct.  The wider spread in spectrum is a known issue with the external resistor implementation due to jitter.  It might improve with the addition of a 10nF external cap in parallel with the 100k precision resistor.  If this still does not satisfy clock requirements of your overall system performance, or CAN communications, we strongly suggest using external crystal as clock source instead.  External crystal would address both clock accuracy and jitter issues.

    Best regards,

    Joseph 

  • 0 in reply to Joseph Casuga
    Prodigy 70 points

    Hi Joseph

    We already tried 10nF external cap near by 100k precision resistor parallelly but the frequency bandwidth is still equal to figure 2.

    We will consider the external crystal solution.

    Thank you

  • 0 in reply to Albert Lu
    TI__Mastermind 41690 points

    Hi Albert,

    Thanks, yes an external crystal should provide both precise clock with very narrow bandwidth.

    Regards,

    Joseph