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TMS320F28377D: McBSP in multichannel mode

luca mattonai
Intellectual 670 points
Part Number: TMS320F28377D

Tool/software:

Hi

I use McBSP in multi channel mode to connect two F28377D board. Till now I have use 16 channels (of 16bit words) and I don't have any synchronization problem or data shift switching on/off any board. Data transfer is managed by two DMA channels one for reception and one for transmission.

Now I have the need of use 32 channels  using (X/R)CERA end (X/R)CERB, but in this case switching on/off the master board (the one that generates frame sync and clock) the data received by the slave may be shifted by 16 position and this is confirmed by the current block indicator.

It will be possible to correct this behaviour?

Best Regards Luca

  • 0
    TI__Guru* 77460 points

    Luca,

    Apologies for the delay, I'm currently traveling and don't have access to any HW to try and reproduce this issue.

    I think from your post, the DMA is not a factor in the behavior, can you confirm that there's not an issue with the DMA that is changing the order of the data, if you read through the CPU things are still incorrect?

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Intellectual 670 points

    Hi Matthew

    I don't know if DMA has some issue. My feeling is that the problem is caused by the factor that using 32 channel is necessary to have two blocks, and the issue depend in wich block is active when the master stop transmission. Master sends a trasmission packet where the first word (channel 0 ) is 0xAAAA and the last  (channel 31) is 0x5555. Switching on/off the master the slave can receive it correctly or shifted. When shifted I can see 0xAAAA in channel 16 and 0x5555 in channel 15, like the block was exchanged. Infact reading the current rx block in the DMA end of transaction interrupt I will find 0 when no shift occur and 1 otherwise. Continuing to on/off the master there is the possibility to get right or wrong data.

    Best regards

    Luca

     

  • 0 in reply to luca mattonai
    Intellectual 670 points

    Hi Matthew

    But if I try to read trough the CPU how can I know the actual channel number?

    Best Regards

    Luca

  • 0 in reply to luca mattonai
    TI__Guru* 77460 points

    Luca,

    If the power is cycled in the middle of a transmission, the receiver is just going to wait for the next clock/message as you experienced.  I think the only way for the receiver to recover is for the master to send a starter message to indicate connection is established as the first communication on power up.  We would need to look for this special message on the receiver side, which would let us know to discard the other half of the terminated message.

    I don't see a way in HW for the receiver to detect that the master got taken off line, so hopefully the above idea will work in your system.

    Best,

    Matthew  

  • 0 in reply to MatthewPate
    Intellectual 670 points

    Hi Matthew

    Thanks for your suggestion, I will try this solution or otherwise instead of 32 word by 16 bit I can use 16 word by 32 bit. I don't have see this problem with a frame of only 16 word.

    best regards

    Luca