TMS320F28377D: DMA destination start address wrong

Hi team

could you please kindly update this question. 

thanks

joe

Hi Joe,

Can you verify in the map file or Expressions view that spiRecdata is actually being placed at 0x01A800? The DATA_SECTION pragma just tells the linker that you want it placed in the TO_CPU1_INTERNALSPI memory range, it doesn't necessarily put it at the beginning of the range. 

Best Regards,

Delaney

Hi Delaney

I debug this issue in customer side, I think the root cause is DMA and SPI operation logic, I do the below change to make the code run properly:

There left one issue need your suggestion.

In SPI slave:

I set DMA(receive) to continues mode, and start DMA(receive)  before timer init, timer is to control GPIO toggle. In SPI master program, GPIO toggle will trigger SPI master send and receive data.

In SPI master:

I set DMA(receive)  to one shot mode, and use GPIO interrupt to trigger SPI master send and enable DMA(receive)  to get SPI data sent by slave.

with the design above, SPI slave and master will sent and receive the data at the same time SPI and DMA work properly. the target is to send 60 words per cycle.

the SPI and DMA configuration code is below:

DMACH6AddrConfig(DMADest,&SpiaRegs.SPIRXBUF);
DMACH6BurstConfig(1,0,1);
DMACH6TransferConfig(29,0,1);

DMACH6WrapConfig(0,0,29,0);

DMACH6ModeConfig(DMA_SPIARX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,
SYNC_DISABLE,SYNC_SRC,OVEFLOW_ENABLE,SIXTEEN_BIT,
CHINT_END,CHINT_ENABLE);

SpiaRegs.SPIFFRX.all=0x2040; // RX FIFO enabled, clear FIFO int
SpiaRegs.SPIFFRX.bit.RXFFIL = 2;

But the receive data will be unstable (wrong order) in some test:

the data order should be 0x0001 0x00FC 0x0002 0x0002... but you can see in this picture, the 0x0001 0x00FC... goes to the 17th position. and sometimes SPI overflow register is set to 1.

Is there any insight for this issue?

Thanks

Joe

Hi Joe,

Joe Ji said:

DMACH6AddrConfig(DMADest,&SpiaRegs.SPIRXBUF);
DMACH6BurstConfig(1,0,1);
DMACH6TransferConfig(29,0,1);

DMACH6WrapConfig(0,0,29,0);

DMACH6ModeConfig(DMA_SPIARX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,
SYNC_DISABLE,SYNC_SRC,OVEFLOW_ENABLE,SIXTEEN_BIT,
CHINT_END,CHINT_ENABLE);

SpiaRegs.SPIFFRX.all=0x2040; // RX FIFO enabled, clear FIFO int
SpiaRegs.SPIFFRX.bit.RXFFIL = 2;

Which device do these settings refer to? The master SPI device or the slave SPI device?

It is good that the burst size (2) equals the SPI RX FIFO trigger level (2/16), and the SPI RX trigger is being used. However, you don't want to have one-shot mode enabled in this case, you want each FIFO level trigger to only transfer 2 words (a single burst) otherwise you will see data loss or strange issues like this.

It may be helpful to look at the 18.3.8 SPI DMA Transfers section of the device TRM for some more information about how to configure the DMA to work with SPI.

Best Regards,

Delaney

Hi Delaney:

The code is to set SPI slave receive data.

Thanks for your suggestion will let customer change the SPI master DMA setting and test.

One problem: I do not see the SPI_ex5 which mentioned in TRM for SPI DMA. the sdk version is 5.02 and 5.04.

Thanks

Joe

Hi Delaney

This solved my issue.

Thanks

joe