Tool/software:
Question 1: Two SRAMs are connected to the EMIF bus. SRAM-1 is accessed in the main loop, while SRAM-2 is accessed in the interrupt. If an interrupt is triggered during the read and write operations on SRAM-1 and SRAM-2 is accessed immediately after entering the interrupt, then how does the EMIF bus operate?
Question 2: DMA is used to operate SRAM-1, and this process takes a relatively long time. During this process, when SRAM-2 is accessed within the interrupt, how does the EMIF bus operate?