Part Number: TMS320F28384D
Other Parts Discussed in Thread: SYSCONFIG, C2000WARE
Tool/software:
When using dual data rate transmission, it has been mentioned in the 2828x TRM that within FSI TX, the data is split into even and odd-numbered bits and sent using both the lanes TXD0 and TXD1.
What happens in the RX module when it receives these dual data lanes?
What I know is that we read the data from the RX buffer.
So, has the data been combined back within the FSI RX core before transferring it to the FSI RX buffer or, should we combine the data ourselves and the data is present in the buffer in a certain way and not combined yet?
If yes, how should we merge the two data lanes at FSI RX?
