Tool/software:
Hi, experts:
I've set up the CMPSS/XBAR/EPWM register to realize ZCD at EPWM4A, but failed changing to EPWM4B.
Ch2 EPWM4B Ch3 CTRIPOUTH OR L Ch4 EPWM4A
I use the CMPSS signal to generate DCBEVT1. And DCBEVT1 generate EPWM4 AQ T1 event to set EPWM4A/B low when T1 on count up.
Here is my configuration:
CMPSS:
XBAR_enableEPWMMux(XBAR_TRIP5, 0x00);
ASysCtl_selectCMPHPMux(ZCD_IL_CMPSS_ASYSCTRL_CMPHPMUX,ZCD_IL_CMPSS_ASYSCTRL_MUX_VALUE);
ASysCtl_selectCMPLPMux(ZCD_IL_CMPSS_ASYSCTRL_CMPLPMUX,ZCD_IL_CMPSS_ASYSCTRL_MUX_VALUE);
CMPSS_enableModule(ZCD_IL_CMPSS_BASE);
CMPSS_configDAC(ZCD_IL_CMPSS_BASE,CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW);
CMPSS_setDACValueHigh(ZCD_IL_CMPSS_BASE+(int16_t)((float32_t)30.0*(float32_t)2048.0/(float32_t)current_max_sense));
CMPSS_setDACValueLow(ZCD_IL_CMPSS_BASE-(int16_t)((float32_t)current_limit *(float32_t)2048.0 /(float32_t)current_max_sense));
CMPSS_configHighComparator(ZCD_IL_CMPSS_BASE, CMPSS_INSRC_DAC );
CMPSS_configLowComparator(ZCD_IL_CMPSS_BASE, CMPSS_INSRC_DAC | CMPSS_INV_INVERTED);
CMPSS_configFilterHigh(ZCD_IL_CMPSS_BASE, 2, 10, 7);
CMPSS_configFilterLow(ZCD_IL_CMPSS_BASE, 2, 10, 7);
CMPSS_initFilterHigh(ZCD_IL_CMPSS_BASE);
CMPSS_configOutputsHigh(ZCD_IL_CMPSS_BASE, CMPSS_TRIPOUT_ASYNC_COMP | CMPSS_TRIP_FILTER);
CMPSS_configOutputsLow(ZCD_IL_CMPSS_BASE, CMPSS_TRIPOUT_ASYNC_COMP | CMPSS_TRIP_FILTER);
CMPSS_clearFilterLatchHigh(ZCD_IL_CMPSS_BASE);
CMPSS_clearFilterLatchLow(ZCD_IL_CMPSS_BASE);
XBAR_setEPWMMuxConfig(XBAR_TRIP5, ZCD_IL_XBAR_MUX_VAL);
XBAR_enableEPWMMux(XBAR_TRIP5, ZCD_IL_XBAR_MUX);
EPWM4:
EPWM_setClockPrescaler(myEPWM4_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
EPWM_setTimeBasePeriod(myEPWM4_BASE, 400);
EPWM_setupEPWMLinks(myEPWM4_BASE, EPWM_LINK_WITH_EPWM_4, EPWM_LINK_TBPRD);
EPWM_setTimeBaseCounter(myEPWM4_BASE, 0);
EPWM_setTimeBaseCounterMode(myEPWM4_BASE, EPWM_COUNTER_MODE_UP);
EPWM_enablePhaseShiftLoad(myEPWM4_BASE);
EPWM_setPhaseShift(myEPWM4_BASE, 1);
EPWM_setSyncInPulseSource(myEPWM4_BASE, EPWM_SYNC_IN_PULSE_SRC_DISABLE);
EPWM_enableSyncOutPulseSource(myEPWM4_BASE, EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC);
EPWM_setCounterCompareValue(myEPWM4_BASE, EPWM_COUNTER_COMPARE_A, 75);
EPWM_setCounterCompareShadowLoadMode(myEPWM4_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setCounterCompareValue(myEPWM4_BASE, EPWM_COUNTER_COMPARE_B, 0);
EPWM_setCounterCompareShadowLoadMode(myEPWM4_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setActionQualifierT1TriggerSource(myEPWM4_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1);
EPWM_setActionQualifierAction(myEPWM4_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(myEPWM4_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(myEPWM4_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
EPWM_setActionQualifierAction(myEPWM4_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(myEPWM4_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(myEPWM4_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
EPWM_setFallingEdgeDeadBandDelayInput(myEPWM4_BASE, EPWM_DB_INPUT_EPWMB);
EPWM_setDeadBandDelayMode(myEPWM4_BASE, EPWM_DB_RED, true);
EPWM_setRisingEdgeDelayCountShadowLoadMode(myEPWM4_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);
EPWM_setDeadBandDelayMode(myEPWM4_BASE, EPWM_DB_FED, true);
EPWM_setFallingEdgeDelayCountShadowLoadMode(myEPWM4_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);
EPWM_selectDigitalCompareTripInput(myEPWM4_BASE, EPWM_DC_TRIP_TRIPIN5, EPWM_DC_TYPE_DCBH);
EPWM_setTripZoneDigitalCompareEventCondition(myEPWM4_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);
EPWM_enableDigitalCompareSyncEvent(myEPWM4_BASE, EPWM_DC_MODULE_B);
EPWM_enableADCTrigger(myEPWM4_BASE, EPWM_SOC_A);
EPWM_enableADCTrigger(myEPWM4_BASE, EPWM_SOC_B);
Best Regards!
