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LAUNCHXL-F280049C:Unable to Receive Data on Slave Microcontroller Using I2C

Daichi Terakado
Prodigy 30 points

Part Number: LAUNCHXL-F280049C
Other Parts Discussed in Thread: C2000WARE

Tool/software:

I am currently using two C2000 F280049C microcontrollers for I2C communication. One is configured as the host (master), and the other as the slave. The host microcontroller is set to transmit data, while the slave is set to receive. However, I am encountering issues where the slave is not receiving data from the host.

Interestingly, when reversing the roles (host as receiver, slave as transmitter), communication works as expected.

Based on the technical reference manual (SPRUI33H), the I2CMDR register is configured as follows:

Host (Master): 0x6620 (binary: 0110 0110 0010 0000)
Slave: 0x4020 (binary: 0100 0000 0010 0000)
However, the 13th bit (SST) in the I2CMDR register seems to be flipped on both microcontrollers. I tried directly writing to the registers, but the SST field does not change.

Additionally:

On the host side, the status register shows the BB (Bus Busy) and ARBL (Arbitration Lost) bits set to 1.
The slave side does not seem to receive any data.
Could you provide guidance on:

Resolving the SST bit issue in the I2CMDR register?
Clearing the BB and ARBL bits on the host?
Whether these issues are directly related to the communication failure, and if solving them would allow successful I2C data transfer?
Any assistance in troubleshooting this problem would be greatly appreciated.

  • 0
    TI__Mastermind 22660 points

    Hi Daichi,

    The expert for this topic is currently out of office for the holidays. Please expect a delay in response. I apologize for any inconvenience.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 30 points

    Hi Delaney,

    Thank you for letting me know. I understand and appreciate the update. I’ll wait patiently for the expert's response once they’re available after the holidays.

    Best regards,
    Daichi

  • 0 in reply to Daichi Terakado
    TI__Mastermind 22660 points

    Hi Daichi,

    Thank you for your patience. You can expect a response from them in the next week.

    Best Regards,

    Delaney

  • 0
    TI__Mastermind 18595 points

    Hi Daichi,

    Apologies for the delay. Please see my answers below:

    Daichi Terakado said:
    Resolving the SST bit issue in the I2CMDR register?

    I2CMDR.STT is only applicable for when the I2C is in controller mode and can only be written to when I2CMDR.IRS=1. Refer to these tables for proper configuration of I2CMDR as well as more information on the I2C operating modes. This table will also be relevant in the next question.

    Daichi Terakado said:
    Clearing the BB and ARBL bits on the host?

    Please note that it sounds like the target is holding the clock low while waiting for the device to transmit or receive the data. Can you confirm if data is being sent properly and its just an issue on the receiving side?

    If you haven't already, please refer to the C2000WARE I2C software examples as a starting point as that could be helpful with initial configurations. 

    Best Regards,

    Aishwarya