[FAQ] TMS320F28P559SJ-Q1: Reading MCAN message from RX FIFOs and RX Buffers

1. Rx FIFO 0 / 1:

The Rx FIFO gives the user 2 separate FIFOs. We can choose them to place incoming CAN messages. For example, a designer may want all 11-bit ID messages to go into Rx FIFO 0, but all 29-bit ID messages to go into Rx FIFO 1. Another example is all messages which are low priority go to Rx FIFO 1, and all high priority messages go to Rx FIFO 0. There is no restriction on how these FIFOs may be used, and there is no requirement that both must be configured. It is acceptable to have only Rx FIFO 0 or Rx FIFO 1.

Each Rx FIFO element contains an 8 byte header, which contains the received ID, data length code (DLC), and many diagnostic flags, such as whether CAN FD was used, or if bit rate switching was enabled. A timestamp is also contained in this header, which allows the designer to know when the packet was received. After the 8 byte header, there is data from the incoming message, up to the maximum allowed data size as described in the Rx FIFO configuration register. If the DLC is greater than the maximum data size described in the configuration register, then the data will be truncated and anything past the maximum data size will be lost. If the DLC is less than the maximum data size allowed, then the designer must not assume that any data after the DLC-described size is valid. The MCAN controller does NOT clear out the data fields. For example, if the Rx FIFO is configured to allow up to 8 bytes, but the DLC is 7 bytes, then the last byte of data in memory is not automatically cleared, and should not be used. It will contain the last value that was written by a previous CAN message.

2. Reading a CAN Message from a Rx FIFO

To read a message from the MCAN FIFO, the process can be broken down into the following steps

1. Determine where the new message is (Rx FIFO 0, Rx FIFO 1, or Rx Buffer)

2. Based on the buffer location of the new message, determine the buffer index and then the start address to read from MCAN RAM

3. Read the MCAN RAM to retrieve the message

4. Acknowledge the new message is read to release the FIFO element for a new message

The process will vary slightly depending on if the new message is in a Rx Buffer or a Rx FIFO; since they are fundamentally different. The FIFOs require the CPU to read a FIFO status register which tells how many new messages are in the FIFO, and what index to start reading at. The buffer requires the CPU to read the New Message Register, which tells the CPU which buffers have unread messages in them. At the end of each read, the CPU must let the MCAN controller know that the new message has been received in order to release the FIFO element. 

3. Rx Buffers

The Rx Buffers allow the designer to place certain CAN messages into a buffer. These buffers contain the same 8 byte header of the Rx FIFOs and the data comes after the header. The only difference is that these buffers do not behave like a FIFO. A SID or XID filter element must explicitly tell the MCAN controller which of the Rx Buffers an incoming message must be sent to. This also means that if a new packet is matched and a filter instructs it to be moved to a Rx Buffer, which already has unread data in it, that data in the buffer is over-written.

4. Reading a CAN Message from a Rx Buffer

Reading a message from the Rx Buffer is similar to the process of reading a message from a Rx FIFO. The difference is that the Rx Buffer index to use for the address calculation comes from the New Data 1/2 registers instead of a Rx FIFO 0/1 Status register.