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TMS320F28379D: DMA_EX_Shared_Periph_ Example Output

Nishka Rao
Intellectual 1536 points

Part Number: TMS320F28379D

Tool/software:

Hi Team,

I'm trying to help a customer understand how to used a shared peripheral ePWM between CPU1 and CPU2. I'm running the example DMA_ex1_shared_Periph using CCS 20.0.0. 

1) I'm not sure what order to load the programs in?

I've started a projectless debug, and connected to C28xx_CPU2 and loaded dma_ex1_shared_periph_cpu2.out

I've loaded dma_ex1_shared_periph_cpu1.out into C28xx_CPU1

However the output I get is only a constant EPWM output as shown below:

2) Additionally, which CPU controls loading the newCMPValue into the EPWM? 

I cant find a EPWM_setCounterCompareValue which calls that variable.

Thanks Team!

  • 0
    TI__Intellectual 1536 points

    Additional question, can an epwm be set up by CPU2 and generate an interrupt by CPU1? 

  • 0
    TI__Mastermind 36526 points

    Hi,

    Our expert for this topic is out of office until next week. Please expect a delayed response. Please allow me to provide some preliminary answers though. 

    Nishka Rao said:
    1) I'm not sure what order to load the programs in?

    CPU1 first and CPU2 second is normally recommended.

    Nishka Rao said:
    2) Additionally, which CPU controls loading the newCMPValue into the EPWM? 

    In the System Control registers, there will be an option to assign ownership of each EPWM module to a particular CPU. Whichever CPU 'owns' the EPWM module will be able to write to the registers for that EPWM module.

    Best Regards,

    Ben Collier

  • 0 in reply to Benjamin Collier
    TI__Mastermind 21518 points

    Hi Nishka, 

    Do you still have further questions?

    Regards,

    Ozino

  • 0 in reply to Ozino Odharo
    TI__Intellectual 1536 points

    Hi Ozino & Ben,

    Thanks for the response :)

    The main question is can an ePWM be set up by CPU2 and generate an interrupt by CPU1? 

     

  • +1 in reply to Nishka Rao
    TI__Mastermind 21518 points

    Hi Nishka,

    2.) In this example, CPU1's DMA updates the ePWM1 CMPA value for the PWM which it owns.

    The newCMPValue is being set in the cpu Timer ISR, on CPU2. Within the Timer ISR routine, the SPI transfer will set the DMA Trigger, done by CPU2.

    The setupDMA routine, on CPU1, sets the newCMPValue as the srcAddress and the EPWM1 CMPA as the destination address. So everytime the DMA is triggered it loads the newCMPValue to the EPWM1 CMPA register. It should be noted that the newCMPValue is assigned to the SHARERAMGS2 data_section which is accessible by both CPUs.

    Regarding the interrupt, you can enable the CPU 1 DMA interrupt in the example by adding the predefined symbol USE_DMA_INTERRUPT.

    Regards,

    Ozino