• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 308 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28388S: Register Address Overlap

Ed Sanders
Genius 4105 points

Part Number: TMS320F28388S

Tool/software:

Greetings,

In a previous post from a couple of months ago titled "CLA_SOFTINT_REGS Address and Location", I received the addresses for the various CLA register sets.  I have just realized that the address for the CLA_SOFTINT_REGS is the same as the PieCtrlRegs, 0x0CE0.  I believe that the PieCtrlRegs is at 0x0CE0 because we are receiving interrupts as expected.  So are the CLA_SOFTINT_REGS at a different address?

Thank you,

Ed

  • 0
    TI__Mastermind 22420 points

    Hi Ed,

    I apologize for my delayed response.

    This is because the CLA and the CPU use a different address space (since CLA addresses only go up to 16-bits whereas CPU addresses can go up to 32-bits). From the CPU perspective, 0x0CE0 refers to the PieCtrlRegs and from the CLA perspective 0x0CE0 refers to the CLA_SOFTINT_REGS. See the C28x Memory Map section in the device datasheet linked here.

    There actually is no real difference between the two registers in CLA_SOFTINT_REGS and the registers of the same name in CLA_ONLY_REGS (if you notice they refer to the same addresses). I am removing the CLA_SOFTINT_REGS from future documentation and software since they are redundant.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Genius 4105 points

    Hi Delaney,

    No worries.  I've had a few delayed responses myself :^).

    In spruii0e, pg 995, section 8.7.2, it states, "The CLA uses the same address to access data and registers as the main CPU.".  The example which follows that statement is for the ePWM.  And the addresses for the peripherals are all within the 16-bit addressing of the CLA.  Are you saying that the PieCntrlRegs is an exception and that the CLA_SOFTINT_REGS, which is only writeable from the CLA is placed at the same address?

    Thank you,

    Ed

  • +1 in reply to Ed Sanders
    TI__Mastermind 22420 points

    Hi Ed,

    I agree these sentences in the TRM are a little confusing. The same addresses can be used by the CPU and the CLA for registers of peripherals that both cores have access to. Different devices have their own cases where the address spaces are used differently between cores, especially for larger devices with a lot of peripherals like the F2838x where address space is more limited. I will make sure this section of the TRM is changed to be more accurate.

    In this specific case, the CLA doesn't have access to the PieCtrlRegs so there is no need to reserve addresses for it in the CLA's (limited) memory space. The addresses can be used to access the CLA_ONLY_REGS instead, which only the CLA has access to. If the CLA accesses registers using the defines in hw_memmap.h (for example like below), the compiler takes care of any address change when compiling for each core.

    For example, if accessing CLA1_ONLY_BASE in a .cla file, the compiler will use the address 0xC00. If you tried to access this register from a C file compiled for the C28x, the compiler would throw an error saying CLA1_ONLY_BASE is not defined, meaning it wouldn't accidentally access the PieCtrlRegs.

    Please upvote this response if it is helpful Slight smile

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Genius 4105 points

    Hi Delaney,

    This makes sense now, especially the phrases, "for registers of peripherals that both cores have access to" and "Different devices have their own cases where the address spaces are used differently between cores".

    Thank you,

    Ed