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TMS320F2800132: Regarding the EPG Module for Serial Bit Stream Generation

Keito Katafuchi
Intellectual 295 points

Part Number: TMS320F2800132

Tool/software:

I am trying to understand the functionality of the EPG module for a particular application I have in mind.
Can you help clarify the following for me?

Does the EGP in SHIFT_xxx_REPEAT mode ping-pong between DATA0 and DATA1?

I mean, when EGP is enabled data in DATA0 is shifted out until BITLENGTH is reached, then it moves to DATA1 and keeps sending.
If BITLENGTH = 10bits, then after 10bits are shifted out from DATA1 it jumps back to shifting out 10bits from DATA0, etc...
This allows for a continuous bitstream (of 10bit segments)

If so, then I understand you write to DATA1 while DATA0 is being shifted out,
and you write to DATA0 while DATA1 is being shifted out?

Am I understanding this correctly?

Table 20-1. SIGGENx Active Register Loading seems to try and explain this, but I didn't quite get it.

  • 0
    TI__Prodigy 710 points

    Hi,
    SIGGENx_DATA1 and SIGGENx_DATA0 constitute a 64-bit bus DATA[63:0] which is  DATATRANIN[63:0]. Say, in SHIFT_RIGHT_REPEAT mode, DATATRAN[63:0] = {0,DATATRANIN[63:1]}, which is then available in DATATRANOUT[7:0] as per the Figure 20-5 in the TRM. After SIGENx_CTL0.BITLENGTH shifts, when you update either DATA1 or DATA0, both their contents get copied into the DATA ACTIVE registers (i.e. DATA[63:0])

    Regards,
    Samritha