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Tool/software:
Hi Champ,
I am asking for my customer.
They are encountering a huge speed difference between running the piece of code (code executing on flash) in CCS debug mode and running in standalone mode by measuring with GPIO toggling. The execution time (running in debug mode / standalone) is different which is very confusing, it's supposed to be the same.
Once they move that specific piece of code to RAM (.ramfunc) with #pragma, there is no time difference in either mode respectively which is expected.
One more info is that actually it will run customer’s bootloader project first, then jump to app code. The piece of measured code is in the app code.
Asking on any ideas or suggestions why there is a time difference when running in debug mode and in standalone mode on the same piece of code ?
Thanks for the input.
Regards,
Johnny
Hi Johnny,
I am looping in the Flash experts to look into your question.
Best Regards,
Delaney
Hi Seamus,
I just realized the expert I re-assigned this to is actually currently out of office. Let me loop in a different expert. I apologize for the delay.
Best Regards,
Delaney
Hi Johnny and Seamus,
Is it running faster in standalone? Can you provide some more information on what exactly is running faster/slower in standalone/debug mode? Is it associated with some peripheral?
Kind regards,
Skyler
Hi Delaney,
No Problem~
Hi Skyler,
My customer observed that significant differences in execution time when running the same ISR code and same CRC code in debug mode compared to stand-along mode. In debug mode, the execution time is much shorter. However, after they moving the ISR and CRC to ramfunc, the execution time becomes consistent across both scenarios.
Best Regards,
Seamus
Hi Seamus,
If moving the ISR an CRC to ramfunc fixes the performance disparity, is there any further action required? Or are you just asking for an explanation of why this may be? When the ISR and CRC functions are not in ramfunc, they aren't copied from flash to RAM during the standard Device_Init() call. Thus, you will likely see decreased performance when running standalone. When loaded to the device in Debug mode, these functions are automatically placed in RAM.
Kind regards,
Skyler
Hi Skyler,
Thanks for reply!
When loaded to the device in Debug mode, these functions are automatically placed in RAM.
Do you mean that when we use CCS debug mode and config the project as boot to Flash, these functions will also automatically place in RAM? If so, I would also like to know why this issue does not occur on the F28004x/3x series.
Best Regards,
Seamus
Hi Seamus,
I was mistaken, these functions are not automatically placed in RAM when loaded in Debug mode. Sorry for the confusion.
When loading the application without the ISR/CRC functions in ramfunc, can you verify the address of the ISR/CRC functions during run-time of the Debug mode? I'd like to see where these functions are executing from. Without placing them in ramfunc, it should be running from flash, but the performance suggests that it may be in RAM somehow.
Kind regards,
Skyler
Hi Skyler,
Thanks for your feedback!
My customer has recorded some experimental data and waveforms.
Please help resolve this issue. Thanks!
Code:
Use debug mode in CCS
Look at PC, it is in Flash.
Ch2 is ISR process time.
However execute the same program after flashing it onto the chip.
The interrupt execution time(ch2) becomes much longer.
Use ramfunc
Check PC, it is in RAM.
Execute the same program after flashing it onto the chip.
The interrupt execution time(ch2) becomes much shorter.
Same as use debug mode in CCS.
Best Regards,
Seamus
Ch2 is ISR process time.
Hi Seamus,
Is this the correct image? This looks like the same execution time as shown below.
The interrupt execution time(ch2) becomes much longer.
What happens in ADC_Value_Update()? Is it executing in RAM or flash? Do you see the same behavior is you place that function in RAM every time?
Kind regards,
Skyler
Hi Skyler,
Sorry for the wrong image..
The first one should look like below image
Use debug mode in CCS
Look at PC, it is in Flash.
Ch2 is ISR process time.
What happens in ADC_Value_Update()? Is it executing in RAM or flash? Do you see the same behavior is you place that function in RAM every time?
Just get ADCs result and the code is as follows.
PC = 0x0861F7. Run in flash.
Place ADC_Value_Update() to RAM by ramfuc. PC = 0x011486
Run debug mode in CCS
Flashing it into chip
Best Regards,
Seamus
Hi Seamus,
Can you provide the linker cmd and .map file associated with this application?
Kind regards,
Skyler
Hi Skyler,
Sorry for being late due to the holiday. Please see the linker cmd and map files in the attachment.
Best Regards,
Seamus
MEMORY { /* BEGIN is used for the "boot to Flash" bootloader mode */ BOOT_RSVD : origin = 0x000002, length = 0x000126 RAMM0 : origin = 0x000128, length = 0x0002D8 RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAMLS0_3 : origin = 0x008000, length = 0x002000 RAMLS4_7 : origin = 0x00A000, length = 0x002000 /* RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 RAMLS2 : origin = 0x009000, length = 0x000800 RAMLS3 : origin = 0x009800, length = 0x000800 RAMLS4 : origin = 0x00A000, length = 0x000800 RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 RAMLS7 : origin = 0x00B800, length = 0x000800 */ RAMLS8 : origin = 0x014000, length = 0x002000 // When configured as CLA program use the address 0x4000 RAMLS9 : origin = 0x016000, length = 0x002000 // When configured as CLA program use the address 0x6000 //RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory //RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory BOOT_ACT_KEY : origin = 0x00C000, length = 0x000010 /* Boot activate key */ RAMGS0 : origin = 0x00C010, length = 0x001FF0 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2_3 : origin = 0x010000, length = 0x004000 // RAMGS2 : origin = 0x010000, length = 0x002000 // RAMGS3 : origin = 0x012000, length = 0x002000 BOOTROM : origin = 0x3F8000, length = 0x007FC0 SECURE_ROM : origin = 0x3F2000, length = 0x006000 RESET : origin = 0x3FFFC0, length = 0x000002 /* Flash sectors */ /* BANK 0 */ // FLASH_BOOT_CODE : origin = 0x080002, length = 0x003FEC /* IAP boot code */ // BOOT_FUNCTION_ID : origin = 0x083FEE, length = 0x000002 /* Function ID record */ // BOOT_VERSION : origin = 0x083FF0, length = 0x000010 /* Boot version record */ FLASH_SIGNATURE : origin = 0x085000, length = 0x000006 /* Signature of app header */ FLASH_APP_HEADER : origin = 0x085006, length = 0x00001A /* App header field */ COMPLIANT_ADDRESS : origin = 0x085020, length = 0x000002 /* Address of compliant table */ FLASH_HEADER_RES : origin = 0x085022, length = 0x0000DE /* Reserved field of app header */ COMPLIANT_TABLE : origin = 0x085100, length = 0x000100 /* Compliant table field */ FLASH_BEGIN : origin = 0x085200, length = 0x000002 /* Flash begin */ FLASH_APP_CODE : origin = 0x085202, length = 0x009DFE /* App code field */ /* BANK 1 */ FLASH_CALIBRATION : origin = 0x08F000, length = 0x001000 /* MFR Data */ FLASH_BANK1_APP : origin = 0x090000, length = 0x00A000 /* Bank1 app ROM field */ /* Reserved */ /* FLASH_BANK2 : origin = 0x0C0000, length = 0x20000 FLASH_BANK3 : origin = 0x0E0000, length = 0x20000 FLASH_BANK4 : origin = 0x100000, length = 0x20000 */ CLATOCPURAM : origin = 0x001480, length = 0x000080 CPUTOCLARAM : origin = 0x001500, length = 0x000080 CLATODMARAM : origin = 0x001680, length = 0x000080 DMATOCLARAM : origin = 0x001700, length = 0x000080 } SECTIONS { codestart : > FLASH_BEGIN, ALIGN(8) .text : > FLASH_APP_CODE, ALIGN(8) .cinit : > FLASH_APP_CODE, ALIGN(8) .switch : > FLASH_APP_CODE, ALIGN(8) .reset : > RESET, TYPE = DSECT /* not used */ .stack : > RAMM1 #if defined(__TI_EABI__) .bss : >> RAMGS0 | RAMGS1 .bss:output : >> RAMGS0 | RAMGS1 .init_array : > FLASH_APP_CODE, ALIGN(8) .const : > FLASH_APP_CODE, ALIGN(8) .data : >> RAMGS0 | RAMGS1 .sysmem : >> RAMGS0 | RAMGS1 .bss:cio : >> RAMGS0 | RAMGS1 #else .pinit : > FLASH_APP_CODE, ALIGN(8) .econst : > FLASH_APP_CODE, ALIGN(8) .ebss : >> RAMGS0 | RAMGS1 .esysmem : >> RAMGS0 | RAMGS1 .cio : >> RAMGS0 | RAMGS1 #endif .ramgs0 : > RAMGS0 .boot_activate : START(_boot_activate) {} > BOOT_ACT_KEY, TYPE = NOINIT .signature : START(_start_of_approm) {} > FLASH_SIGNATURE .appheader : > FLASH_APP_HEADER .compliantaddress : > COMPLIANT_ADDRESS .headerreserved : > FLASH_HEADER_RES .complianttable : START(_start_of_complianttable), {} > COMPLIANT_TABLE .approm : START(_start_of_appcode), END(_end_of_approm) {} > FLASH_APP_CODE .calibration : START(_start_of_calibration), END(_end_of_calibration) { . += SIZE(FLASH_CALIBRATION); } > FLASH_CALIBRATION .appbank1 : START(_start_of_appbank1), END(_end_of_appbank1) { . += SIZE(FLASH_BANK1_APP); } > FLASH_BANK1_APP .TI.ramfunc : { -l FAPI_F28P55x_COFF_v4.00.00.lib Sine_Process.obj Math_Table.obj(.econst) } LOAD = FLASH_APP_CODE, RUN = RAMGS2_3, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), ALIGN(8) cla1ToCpuMsgRAM : > CLATOCPURAM cpuToCla1MsgRAM : > CPUTOCLARAM .scratchpad : >> RAMLS4_7 .bss_cla : >> RAMLS0_3 Cla1Prog : LOAD = FLASH_APP_CODE, RUN = RAMLS4_7, LOAD_START(_ClaFuncsLoadStart), LOAD_SIZE(_ClaFuncsLoadSize), RUN_START(_ClaFuncsRunStart), ALIGN(8) .const_cla : LOAD = FLASH_APP_CODE, RUN = RAMLS0_3, LOAD_START(_ClaConstLoadStart), LOAD_SIZE(_ClaConstLoadSize), RUN_START(_ClaConstRunStart), ALIGN(8) } //---------------- END LINE -----------------------------------------------------------------------
Hi Seamus,
Is the _FLASH symbol defined in the project? Are you configuring the flash waitstates at any point of the application or bootloader?
Kind regards,
Skyler
Hi Skyler,
Thanks for the reply!
Yes, they have opened the predefine symbol _FLASH and they don't config any wait state in their code.
Best Regards,
Seamus
Hi Skyler,
Do they need to write their own wait state in the program? Can you guide us on how to add wait state?
Best Regards,
Seamus
Hi Seamus,
The waitstates should be set in the Flash_initModule() function which gets called within Device_Init() as long as the _FLASH symbol is defined. Thus, I don't think that's the issue here. I'm going to discuss internally with other experts and give you response within the next day.
Kind regards,
Skyler
Hi Skyler,
Thanks for your help! Please keep me posted.
Best Regards,
Seamus
Hi Skyler,
Do you have any new findings on this issue?
Best Regards,
Seamus
Hi Seamus,
Apologies for the delay. When you load the program to the device via CCS, can you try calling Flash_disableCache() and Flash_disablePrefetch() after device initialization? Additionally, make sure that Flash_initModule() is not being called after you disable the cache and prefetch mechanisms.
Kind regards,
Skyler
Hi Skyler,
We found that there is nothing written in the InitFlash() function, now I just suggest customers to use Flash_initModule() instead of InitFlash().
I want to know:
1. Are these two funcs exactly execute the same thing, with only differences in API and bit field style?
2. When will we complete this InitFlash() function in P55 ?
Best Regards,
Seamus
Hi Seamus,
1. Yes, generally the only difference between initFlash() and Flash_initModule() is the driverlib vs bitfield style.
2. These functions will be completed in the next C2000Ware release.
Does using Flash_initModule() in the application create consistent ISR performance when loading via CCS and the bootloader? Or does that still need to be investigated?
Kind regards,
Skyler
Hi Skyler,
Yes, after changing function from initFlash() to Flash_initModule() the issue is resolved. We didn't go into initFlash() before you suggest to calling Flash_disableCache() and Flash_disablePrefetch() after device initialization. Thanks for your help!
Best Regards,
Seamus