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TMS320F28386D: Config CMPSS in async mode for Peak Current Mode Control

Benito Carotenuto
Intellectual 366 points

Part Number: TMS320F28386D
Other Parts Discussed in Thread: SYSCONFIG, C2000WARE

Tool/software:

Dear experts,

I am programming the CMPSS4 on the TMS320F28386D device in asynchronous mode to implement the peak current mode control.

I am not able to disable the latch in the CMPSS in order to get the asynchronous mode.

Here below the configuration of my CMPSS4

As you can see, the asynchronous path has been selected (CTRIPOUTxSEL = 0, CTRIPxSEL = 0).

Every time the analog signal overcomes the threshold, the corresponding PWM is tripped, accordingly. 

However, when the analog signal decreseas up to 0, the PWM remains tripped because the output of the comparator is latched.

Finally, If i clear the bit COMPHLATCH by means of the bit HLATCHCLR, the trip of the PWM is removed.

Therefore, it seems that despite my configuration the latch is always enabled....

Why the latch of the CMPSS can not be by-passed?

Waiting for a feedback,

regards,

Benito

  • 0
    TI__Expert 5600 points

    Hello,

    If the latched path is desired, clear COMPSTS latch using COMPSTSCLR. More info on LATCHCLR can be found in device TRM: https://www.ti.com/lit/ug/spruii0f/spruii0f.pdf, Chapter 22.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals

  • 0 in reply to Stevan Duraskovic
    Intellectual 366 points

    Dear Stevan,

    the latched path is unwanted.

    Benito Carotenuto said:
    I am not able to disable the latch in the CMPSS in order to get the asynchronous mode.

    I want to implement the PEAK CURRENT MODE control. Therefore, the CMPSS has to be configured in asynchronous mode.

    Benito Carotenuto said:
    Finally, If i clear the bit COMPHLATCH by means of the bit HLATCHCLR, the trip of the PWM is removed.

    My PWM is configured in cycle-by-cycle mode. 

    Moreover, I observed by means of the oscilloscope that the signal CTRIPOUTH returns to low if the analog signal decreses to 0.

    So, my  CMPSS asynchronous configuration is correct....

    However, in order to restore the PWM and remove the tripping, I have to clear the bit COMPHLATCH by means of the bit HLATCHCLR.

    Without this clear, the PWM remains tripped....

    Any other suggestions, please?

    Benito

  • 0 in reply to Benito Carotenuto
    TI__Expert 5600 points

    Hello Benito,

    I understand what you meant now. Did you set up your sysconfig like this?  You should not have latched output in this case then. Also, there is CMPSS example for asynchronous trip in C2000Ware: C:\ti\c2000\C2000Ware_5_03_00_00\driverlib\f2837xs\examples\cpu1\cmpss

  • 0 in reply to Stevan Duraskovic
    Intellectual 366 points

    Dear Steven,

    thank you for your reply.

    Stevan Duraskovic said:
    Did you set up your sysconfig like this?

    Yes, I did. As you can see in my configuration, the register COMPCTL.CTRIPOUTHSEL=0x0 and COMPCTL.CTRIPHSEL=0x0.

    This is the bit field value to configure the asynchronous comparator. 

     

    Stevan Duraskovic said:
    Also, there is CMPSS example for asynchronous trip in C2000Ware: C:\ti\c2000\C2000Ware_5_03_00_00\driverlib\f2837xs\examples\cpu1\cmpss

    I will study this example and I will get back to you for a feedback.

    Thank you very much.

    Benito