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TMS320F28P650DK: Transmit odd number of Bytes from UART FIFO by DMA

Leo Wu
Intellectual 1370 points
Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: C2000WARE

Tool/software:

Hi experts,

My customer wants to use DMA to transmit odd number of Bytes data (for example 9 Bytes) from UART FIFO.

I found that the DMA must transfer data in multiples of 2 Bytes. For UART, the FIFO trigger level is 2, 4, 8, 12, 14 Bytes.

I refer to this link and find that there is a method to workaround this issue.

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/967094/tms320f28388d-no-clear-path-to-achieve-efficient-data-handling-with-cm-uart

The method is that users can start a timer counting when DMA is triggered to generate a delay. The delay should be the time of DMA transmitting and the remaining 1 Byte of data transmitting. After delay, the user can get the last 1 Byte data. But it need CPU.

Are there any other method to transmit odd number of Bytes from UART FIFO by DMA?

Thanks,

Leo

  • 0
    TI__Mastermind 19595 points

    Hi Leo,

    The key with using DMA and UART together is that the burst size of the DMA channel needs to be equal to the FIFO trigger level (since you want to trigger the DMA to move over x number of bytes when x spaces are available/full in the UART FIFO). The fact that there is no 1/16 FIFO trigger level for UART is indeed a known issue that we are planning to fix in the UART peripheral for future devices. Is the customer just trying to use the UART to transmit an odd number of bytes (not receive)?

    The CPU timer method could work, however my hesitation with that is: the DMA doesn't know for sure there are enough spaces available in the TX FIFO if it isn't being triggered by the UART itself. This is also assuming the timing of UART transmits are deterministic, which I know for the SCI peripheral is not the case. For the UART peripheral, this is something I would have to check with the design team on. If the timing is deterministic, this could work. They would also need to make sure there is only one DMA channel being used, because timing could change if channel priority causes the UART TX DMA channel to have to wait for other channels to finish their transactions before moving data into the UART data register.

    Some other suggestions:

    1. Use the DMA to move over the first 8 bytes (or all but 1 byte) with the UART trigger and write the very last byte to the UART data register in the CPU in the end-of-transfer DMA interrupt. This would add a little bit of extra CPU usage, but the majority of the operation would be done by the DMA.
    2. Transmit an even number of bytes and configure the receiving device to ignore the last byte received (if possible).
    3. Switch to using the LIN peripheral in SCI mode. This peripheral is present on the F28P65x, has DMA access, and can trigger the DMA with single bytes. We have 2 examples in C2000ware that show how to use LIN SCI mode + DMA to transmit and receive (lin_ex3_sci_dma - using multibuffered mode (similar to FIFO) and lin_ex7_sci_dma_single_buffer - uses single-buffered mode (similar to non-FIFO).

    Let me know if any of these other solutions would be feasible for the customer. If not, I will contact the design team to look into the CPU timer solution.

    Best Regards,

    Delaney