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Stop PWM synchronously



I use F28035 to implement PWM motor drive.

When the motor is disabled, PWM outputs should be in high impedance mode. I configured Trip-Zone module accordingly, and once the motor should be disable, execute TZFRC.OST=1. It works fine; generally, disabling is not synchronous with PWM and can occur at any moment within PWM cycle.

Now I am required to synchronize disabling with PWM cycle. In other words, despite assignment TZFRC.OST=1 occurs at arbitrary moment within PWM cycle, PWM outputs should go high impedance only in the beginning of the next PWM cycle.

Does anybody know how to achieve this?

Thanks in advance. 

  • Hi Sasha,

    Apologies for the problems you are having getting the PWMs to shut off synchronously.  As you have discovered, the TZ module was designed to work asynchronously.  A typical use case scenario would involve a system fault, in which case you absolutely need to get the PWMs off-line as soon as possible.

    However, I think there may be a way to achieve the desired behavior.  Do you have any spare PWM outputs?  Depending on which version of the '35 you are using, you should either have 12 or 14 PWM outputs.  If you have a spare channel, I would suggest using it as a synchronous disable signal.  Program the duty cycle for this channel to normally be 100%.  When you want to disable your PWM outputs, immediately program this duty cycle to be 0%.  Since the PWM channel registers are double buffered, you can program the ePWM module so that this value won't get picked up until the start of the next PWM cycle.  At this boundary, the PWM output will immediately transition to zero since the duty cycle is 0%.  Wrap this signal back into a TZx input pin, which should then disable the remaining PWM outputs before they can affect any changes on your inverter transistors.

    Good Luck!

    -Dave

     

  • Hi Dave,

    Thank you very much for your answer. We use 64-pin package with 6 PWM's. One PWM is still free; however, we'd like to keep it for implementing additional DAC in the future. Anyway, we will implement your solution, if no else is possible.

    Meanwhile, I am looking into Digital Compare submodule. Seems, its blanking window can provide synchronous switch. Yet, I cannot figure out how to activate it programmatically, similar to TZFRC.OST=1. Can you give a hint?

    Thank you,

    Sasha

     

     

  • Hi Sasha,

    I think this idea is worth pursuing, although admittedly I have not tried this before.

    To make this work, try programming the DCFOFFSET register to zero, and program the DCFWINDOW register to one count less than the PWM period value.  This should block any disable event from getting through until right before the start of the next PWM cycle.

    I hope this works!

  • That looks straightforward. However, do you know how to fire event programmatically, similar to TZFRC.OST=1?

  • Sasha,

    I believe you can do this with the TZDCSEL register.  This register qualifies the DCA high and low signals, as well as the DCB high and low signals to generate the DCAEVTx and DCBEVTx signals.  These output signals are the ones that are passed to the blanking window circuit.  The TZDCSEL register is partitioned as four 3-bit fields to control the DCAEVTx and DCBEVTx signals.  The binary value of %000 for each bit field will disable the event altogether.

    So here is a proposed solution to layer on top of my last response:

    Set one of theTZx pins to generate a continuous fault.

    Program the appropriate TZDCSEL bit field to %000 (disable the TZx signal from getting through)

    When you want to turn off the PWMs, program the appropriate TZDCSEL bit field to something other than %000 to allow the TZx bit to get through with the desired polarity.

    Assuming you have programmed the blanking window as specified in my last response, This should delay the trip until the end of the current PWM cycle.

    Good Luck,

    Dave

     

  • Dave,

    I appreciate your help greatly. I will be able to give a try tomorrow.

    However, I don't see how the method works. In this method, DCAEVT signal is constant, and actual switch is due to TZDCSEL register. The TZDCSEL register is part of Trip Zone module, but the Trip Zone is asynchronous; therefore I guess the outputs would switch to high impedance immediately with changing TZSCSEL.

    By the way, synchronous disable is common request, if a motor control or power supply implements zero voltage or zero current switch strategy - in this case, asynchronous disable simply burns out the transistors. I think, it would be great to provide some common example for TI community.

    Thank you,

    Sasha 

  • Sasha,

    Is the motor stop signal internal SW or externally generated?  If it is internal, you could modify your control loop ISR to do something similar to what Dave suggested.  Instead of using an additional PWM to cause a trip condition, you could set the compare values for your PWM modules to 0 duty values using the ISR instead.  They would all get reloaded at the same time on the next PWM cycle.

    I have not tried this myself but I think it should work.

    Regards,
    Daniel