TMS320F28388D: Benchmark information for ADC and C28x

Hi Connor,

The ADC timing diagrams in the F28388D datasheet section 7.11.2.3.9 illustrate how the throughput is derived.  First stage is data sampling time (SH) which is a function of the input network.  A well-matched input, which has signal source that has minimum source impedance can have a minimum SH time, for higher impedance sources, SH needs to be higher for proper signal settling.  Second stage is the quantization, which is dependent on the ADC speed.   The maximum ADC CLK speed is 50MHz and this provides the fastest conversion time.  Considering the best case scenarios for 16-bit mode, the maximum throughput is 1MSPS.  For 12-bit, maximum throughput is 3.5MSPS.  The ADC throughput will obviously decrease if the optimum conditions are not used.

There is an application note on benchmarking showing how the different functions in C28 compare with ARM.  Here is the link.

Regards,

Joseph