TMS320F28379D: TMS320F28379D

Aditya Malwade

Tool/software:

Hi,

I am using nested interrupts in the F28379D microcontroller. After enabling nested interrupts, the priority order is set as follows:

Highest Priority: ePWM12 (Pievector group 3)
Next Priority: Pievector group 1 for ADC and Timer 0
Lowest Priority: Pievector group 9 for SCI-A, SCI-B, and CAN-B.

All interrupts work accordingly with the set priorities. However, when ePWM12 is set for 156 µs, there is a ±2 µs shift observed in every cycle. But when only ePWM12 is used, it maintains a steady 156 µs. Below is the code for interrupt and ePWM12 initialization:

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM12_INT = &epwm12_isr; // Control ISR
PieVectTable.EPWM1_INT = &epwm1_isr; // ePWM 1 ISR
PieVectTable.EPWM11_INT = &epwm11_FastISR; // DAC
PieVectTable.XINT1_INT = &xint1_isr; // XINT 1
PieVectTable.XINT2_INT = &xint2_isr; // XINT 2
PieVectTable.ADCD1_INT = &adcd1_isr; // ADC D1 ISR
PieVectTable.TIMER0_INT = &cpu_timer0_isr; // Timer 0
PieVectTable.TIMER1_INT = &cpu_timer1_isr; // I2T PROTOCOL
PieVectTable.TIMER2_INT = &cpu_timer2_isr; // Timer 2
PieVectTable.SCIA_RX_INT = &sciaRxFifoIsr; // SCI - A RX ISR
PieVectTable.SCIB_RX_INT = &scibRxFifoIsr; // SCI - B RX ISR
PieVectTable.CANB0_INT = &canbISR; // CAN - B RX ISR
EDIS; // This is needed to disable write to EALLOW protected registers

// Enable PIE interrupts
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable PIE
PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // Enable XINT 1 interrupt
PieCtrlRegs.PIEIER1.bit.INTx5 = 1; // Enable XINT 2 interrupt
PieCtrlRegs.PIEIER1.bit.INTx6 = 1; // Enable ADC interrupt
PieCtrlRegs.PIEIER1.bit.INTx7 = 1; // Enable Timer0 interrupt

PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // Enable ePWM1 interrupt
PieCtrlRegs.PIEIER3.bit.INTx11 = 1; // Enable ePWM11 interrupt
PieCtrlRegs.PIEIER3.bit.INTx12 = 1; // Enable ePWM12 interrupt

PieCtrlRegs.PIEIER9.bit.INTx1 = 1; // Enable SCI-A interrupt
PieCtrlRegs.PIEIER9.bit.INTx3 = 1; // Enable SCI-B interrupt
PieCtrlRegs.PIEIER9.bit.INTx7 = 1; // Enable CAN-B interrupt

PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;
PieCtrlRegs.PIEIFR3.all = ISRS_GROUP2;
PieCtrlRegs.PIEIFR9.all = ISRS_GROUP3;
EINT; // Enable Global interrupt INTM
ERTM;

ePWM12 initalization

//
// Setup TBCLK
//
EPwm12Regs.TBPRD = 7812; // 78.125us execution time 12.8KHz
EPwm12Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm12Regs.TBCTR = 0x0000; // Clear counter

//
// Set Compare values
//
EPwm12Regs.CMPA.bit.CMPA = 2000; // Set compare A value
EPwm12Regs.CMPB.bit.CMPB = 2000; // Set Compare B value

//
// Setup counter mode
//
EPwm12Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm12Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm12Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm12Regs.TBCTL.bit.CLKDIV = TB_DIV1; // CLOCK DIVISION BY ONE

//
// Setup shadowing
//
EPwm12Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // SHADOW A MODE
EPwm12Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // SHADOW B MODE
EPwm12Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load A on Zero
EPwm12Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // LOAD B MODE ZERO

//
// Set actions
//
EPwm12Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on event A, SET AT UP COUNT
EPwm12Regs.AQCTLA.bit.CAD = AQ_SET; // Clear PWM1A on event A, CLEAR AT DOWN COUNT

EPwm12Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, SET AT UP COUNT
EPwm12Regs.AQCTLB.bit.CBD = AQ_SET; // Clear PWM1B on event B, CLEAR AT DOWN COUNT

// Interrupt where we will change the Compare Values
EPwm12Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm12Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm12Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1ST event

CPU clock is 200MHz

Regards,

Aditya

over 1 year ago

0 Delaney Woodward over 1 year ago

TI__Mastermind 22600 points

Hi Aditya,

Just to clarify, are you saying you are using the ePWM12, ADCD1, timer 0, SCIA, SCIB, and CANB interrupts together? The hardware configured priorities of these interrupts according to the ePIE table (without nesting) would be:

1. ADCD1 (highest priority)

2. TIMER0

3. EPWM12

4. SCIA_RX

5. SCIB_RX

6. CANB_0 (lowest priority)

And you are changing the priorities according to the following scheme, is that correct?

1. EPWM12 (highest priority)

2. ADCD1

3. TIMER0

4. SCIA_RX

5. SCIB_RX

6. CANB_0 (lowest priority)

If so, depending on the timing of the interrupts coming in, if an EPWM12 interrupt comes in at the same time as/during either an ADCD1 or TIMER0 interrupt, the CPU will branch to the interrupt with the higher hardware priority first before actually entering the ISR of the EPWM12 interrupt. For example, say the TIMER0 and EPWM12 interrupts are both pending when the CPU has just completed a previous ISR. The CPU will:

Branch to the TIMER0 ISR
Execute masking instructions of the appropriate IER/PIEIER registers
Enable interrupts globally
Branch to the EPWM12 ISR and execute to completion
Return to the TIMER0 ISR and finish completion

All of this ISR branching requires clock cycles for vector fetch, context save/restore, and masking instructions. This should potentially be why you are seeing this shift. Even more branching is required if the ADCD1 interrupt was also pending at the same time. One way to reduce the amount of nesting occurring would be to use the TIMER1 or TIMER2 interrupts instead, if you are fine with the timer interrupt having the lowest priority. This way, the EPWM12 doesn't need to nest inside of it.

Please upvote any responses that were helpful to you

Best Regards,

Delaney

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TMS320F28379D: TMS320F28379D