F28335 : cpu frequency issue

wauters gregory

Prodigy 160 points

hi all,

On my project, the CPU is set to work at 30MHz. When I do the piece of code below, it takes 5µsec:

-1.5µsec to do the i++

-1.5µsec to toggle the I/O

-2µsec to store the register value

       for(i=0; i < 8192; i++)
    {
        GpioDataRegs.GPASET.bit.GPIO2   = 1;
        g_AdcMesure[i]    = AdcRegs.ADCRESULT0;
        GpioDataRegs.GPACLEAR.bit.GPIO2 = 1;
    }

#define DSP28_DIVSEL     3 // Enable /1 for SYSCLKOUT
#define DSP28_PLLCR    0 // PLL is bypassed in this mode

void InitSysCtrl(void)
{

   // Disable the watchdog
   DisableDog();

   // Initialize the PLL control: PLLCR and DIVSEL
   InitPll(DSP28_PLLCR,DSP28_DIVSEL);

   // Initialize the peripheral clocks
   InitPeripheralClocks();
}

It is very very slow, I can t figure out what is going wrong.

thanks a million to anybody 's help,

greg.

over 14 years ago

0 wauters gregory over 14 years ago

Prodigy 160 points

The reasons seems to be that my program is executed from flash and not from RAM. If I do the following change I do get the timing I am expected :

.cinit : > FLASHA PAGE = 0

.pinit : > FLASHA PAGE = 0

.text : > FLASHA PAGE = 0

.cinit              : > RAML3      PAGE = 0
   .pinit              : > RAML3      PAGE = 0
   .text               : > RAML3      PAGE = 0

halas,It only works when my emulator is plugged in. I supposed I need to copy the program from flash to ram ???. Has somebody faced this issue before ?.

greg

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */
   FLASHC      : origin = 0x328000, length = 0x008000     /* on-chip FLASH */
   FLASHA      : origin = 0x300000, length = 0x020000     /* on-chip FLASH */

   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
   CSM_PWL1    : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA. CSM password locations in FLASHA */
   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */

   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */
   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   DATA_RAM    : origin = 0x00C000, length = 0x004000     /* on-chip RAM block L4 to L7 */
   ZONE7        : origin = 0x0200000, length = 0x010000    /* XINTF zone 7 - data space */
   FLASHB      : origin = 0x330000, length = 0x008000     /* on-chip FLASH */

}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/

SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA      PAGE = 0
   .pinit              : > FLASHA      PAGE = 0
   .text               : > FLASHA      PAGE = 0

   codestart           : > BEGIN       PAGE = 0
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0

   csmpasswds          : > CSM_PWL1    PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > DATA_RAM    PAGE = 1
   .ebss               : > DATA_RAM    PAGE = 1
   .esysmem            : > DATA_RAM    PAGE = 1
   AdcMesure           : > DATA_RAM    PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA      PAGE = 0
   .switch             : > FLASHA      PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHC      PAGE = 0                  /* Math Code */
   IQmathTables        : > IQTABLES    PAGE = 0, TYPE = NOLOAD
   IQmathTables2       : > IQTABLES2   PAGE = 0, TYPE = NOLOAD
   FPUmathTables       : > FPUTABLES   PAGE = 0, TYPE = NOLOAD

   firldb   align(0x800)     > RAML0   PAGE = 0
   firfilt    align(0x800)     > RAML1   PAGE = 0
   coefffilt align(0x800)    > RAML2   PAGE = 0


   /* Allocate 0x400 of XINTF Zone 7 to storing data */
   AdcTraitement    : > ZONE7,    PAGE = 1

   /* .reset is a standard section used by the compiler. It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed. Thus the default type is set here to */
   /* DSECT */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD

}

0 wauters gregory over 14 years ago

Prodigy 160 points

The reasons seems to be that my program is executed from flash and not from RAM. If I do the following change I do get the timing I am expected :

.cinit : > FLASHA PAGE = 0

.pinit : > FLASHA PAGE = 0

.text : > FLASHA PAGE = 0

.cinit              : > RAML3      PAGE = 0
   .pinit              : > RAML3      PAGE = 0
   .text               : > RAML3      PAGE = 0

halas,It only works when my emulator is plugged in. I supposed I need to copy the program from flash to ram ???. Has somebody faced this issue before ?.

greg

0 Brett Larimore over 14 years ago in reply to wauters gregory

TI__Guru 57255 points

Greg,

It looks like you have a section called ramfuncs defined in your linker command file which will load code from FLASHD and place it in RAML0 at run time. You just need to put your code into this section. More can be found in the TMS320C28x C/C++ Compiler User Guide (spru514).

For example:

#pragma CODE_SECTION(GPIO_loop, "ramfuncs");

void GPIO_loop()
{
    for(i=0; i < 8192; i++)
    {
        GpioDataRegs.GPASET.bit.GPIO2   = 1;
        g_AdcMesure[i]    = AdcRegs.ADCRESULT0;
        GpioDataRegs.GPACLEAR.bit.GPIO2 = 1;
    }
}

Thanks,
Brett

0 wauters gregory over 14 years ago in reply to Brett Larimore

Prodigy 160 points

Thanks a lot, it works grand now !

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F28335 : cpu frequency issue