TIDM-02000: Query Regarding Slope Compensation in 3kW DC/DC Converter Design (Based on TIDM-02000)

Hello, 

I think your issue is here:

Maybe that is what you meant by "the pink gating signal fails to turn off earlier than the light green gating signal, as expected"?

In any case, if you followed TIDM-02000, then the CMPSS module generates the trip events to the PWM. The PWM action qualifier and trip zone logic will then switch its outputs based on that trip event to achieve the phase shift. It is true that the ramp slope of the CMPSS will impact the timing of the trip event. However, making the ramp faster (increasing slope value) may not be the answer. 

Previously when we have seen similar issues, there are two possible culprits:

- Incorrect configuration of the CMPSS trip logic. Specifically the digital filter settings in the CMPSS. Incorrect filter setting can filter the trip event to the PWM, causing wrong PWM outputs. Can you share your CMPSS configuration?

- Incorrect PWM action qualifier or trip-zone configuration. Incorrect AQ/TZ settings can cause incorrect PWM outputs. Can you share your AQ and TZ PWM settings?

Thank you for your detailed response and guidance. Based on your suggestion, I’ve reviewed our CMPSS configuration and PWM Action Qualifier (AQ) and Trip Zone (TZ) logic settings. Below are the relevant configurations from our design:

1. We use the following configuration for the CMPSS module (specific to the phase-shifted full-bridge control logic:

void PSFB_HAL_initCmpssPCMC(void)
{
    CMPSS_enableModule(PSFB_PCMC_OCP_CMPSS_BASE);
    CMPSS_configHighComparator(PSFB_PCMC_OCP_CMPSS_BASE, CMPSS_INSRC_DAC);
    CMPSS_configLowComparator(PSFB_PCMC_OCP_CMPSS_BASE, CMPSS_INSRC_DAC);

    ASysCtl_selectCMPHPMux(PSFB_PCMC_OCP_CMPSS_ASYSCTRL_CMPHPMUX, PSFB_PCMC_OCP_CMPSS_ASYSCTRL_MUX_VALUE);
    ASysCtl_selectCMPLPMux(PSFB_PCMC_OCP_CMPSS_ASYSCTRL_CMPLPMUX, PSFB_PCMC_OCP_CMPSS_ASYSCTRL_MUX_VALUE);

    CMPSS_configDAC(PSFB_PCMC_OCP_CMPSS_BASE, CMPSS_DACREF_VDDA | CMPSS_DACVAL_PWMSYNC | CMPSS_DACSRC_RAMP);

    EALLOW;
    HWREGH(PSFB_PCMC_OCP_CMPSS_BASE + CMPSS_O_COMPDACCTL) =
        (HWREGH(PSFB_PCMC_OCP_CMPSS_BASE + CMPSS_O_COMPDACCTL) &
         ~(CMPSS_COMPDACCTL_RAMPSOURCE_M)) | (8);
    EDIS;

    CMPSS_setRampDecValue(PSFB_PCMC_OCP_CMPSS_BASE, PSFB_SLOPE_INITIAL);
    CMPSS_setMaxRampValue(PSFB_PCMC_OCP_CMPSS_BASE, PSFB_PCMC_DAC_INIT);
    CMPSS_setDACValueLow(PSFB_PCMC_OCP_CMPSS_BASE, PSFB_OCP_DAC_INIT);

    CMPSS_configFilterLow(PSFB_PCMC_OCP_CMPSS_BASE, PSFB_OCP_SAMPLE_PRESCALE, PSFB_OCP_SAMPLE_WINDOW, PSFB_OCP_THRESHOLD);
/* 
Where
#define PSFB_OCP_SAMPLE_PRESCALE 2
#define PSFB_OCP_SAMPLE_WINDOW 10
#define PSFB_OCP_THRESHOLD 7  
*/
    CMPSS_configFilterHigh(PSFB_PCMC_OCP_CMPSS_BASE, 0, 4, 4);

    CMPSS_initFilterHigh(PSFB_PCMC_OCP_CMPSS_BASE);
    CMPSS_initFilterLow(PSFB_PCMC_OCP_CMPSS_BASE);

    CMPSS_configOutputsHigh(PSFB_PCMC_OCP_CMPSS_BASE, CMPSS_TRIP_FILTER | CMPSS_TRIPOUT_FILTER);
    CMPSS_configOutputsLow(PSFB_PCMC_OCP_CMPSS_BASE, CMPSS_TRIP_FILTER | CMPSS_TRIPOUT_FILTER);

    CMPSS_clearFilterLatchHigh(PSFB_PCMC_OCP_CMPSS_BASE);
    CMPSS_clearFilterLatchLow(PSFB_PCMC_OCP_CMPSS_BASE);
}

2. WM Action Qualifier (AQ) and Trip Zone (TZ) Configuration

void PSFB_HAL_setupBoardProtection(uint32_t base1, uint32_t base2, uint32_t base3)
{
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX_INIT);

    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX01_CMPSS1_CTRIPL);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX01);

    EPWM_selectDigitalCompareTripInput(base1, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH);
    EPWM_selectDigitalCompareTripInput(base2, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH);
    EPWM_selectDigitalCompareTripInput(base3, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH);

    EPWM_setTripZoneDigitalCompareEventCondition(base1, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneDigitalCompareEventCondition(base2, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneDigitalCompareEventCondition(base3, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);

    EPWM_setDigitalCompareEventSource(base1, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
    EPWM_setDigitalCompareEventSource(base2, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
    EPWM_setDigitalCompareEventSource(base3, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);

    EPWM_enableTripZoneSignals(base1, EPWM_TZ_SIGNAL_DCBEVT1);
    EPWM_enableTripZoneSignals(base2, EPWM_TZ_SIGNAL_DCBEVT1);
    EPWM_enableTripZoneSignals(base3, EPWM_TZ_SIGNAL_DCBEVT1);

    EPWM_setTripZoneAction(base1, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
    EPWM_setTripZoneAction(base1, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);

    EPWM_setTripZoneAction(base2, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
    EPWM_setTripZoneAction(base2, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);

    EPWM_setTripZoneAction(base3, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
    EPWM_setTripZoneAction(base3, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);

    EPWM_clearTripZoneFlag(base1, (EPWM_TZ_FLAG_OST | EPWM_TZ_FLAG_DCAEVT2 | EPWM_TZ_FLAG_DCBEVT1));
    EPWM_clearTripZoneFlag(base2, (EPWM_TZ_FLAG_OST | EPWM_TZ_FLAG_DCAEVT2 | EPWM_TZ_FLAG_DCBEVT1));
    EPWM_clearTripZoneFlag(base3, (EPWM_TZ_FLAG_OST | EPWM_TZ_FLAG_DCAEVT2 | EPWM_TZ_FLAG_DCBEVT1));

    EPWM_forceTripZoneEvent(PSFB_FB_PWM1_BASE, EPWM_TZ_FORCE_EVENT_OST);
    EPWM_forceTripZoneEvent(PSFB_FB_PWM2_BASE, EPWM_TZ_FORCE_EVENT_OST);
    EPWM_forceTripZoneEvent(PSFB_SR_PWM_BASE, EPWM_TZ_FORCE_EVENT_OST);
}

void PSFB_HAL_setupFBPWMs(uint32_t base1, uint32_t base2,
        uint16_t pwm_period_ticks, uint16_t pwm_db_ticks_ls,
        uint16_t pwm_db_ticks_hs)
{
    EALLOW;

    EPWM_setPeriodLoadMode(base1, EPWM_PERIOD_DIRECT_LOAD);
    EPWM_setTimeBasePeriod(base1, pwm_period_ticks);
    EPWM_setTimeBaseCounter(base1, 0);
    EPWM_setPhaseShift(base1, 0);
    EPWM_setTimeBaseCounterMode(base1, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_setClockPrescaler(base1, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_A, 0);
    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_B, 0);
    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_C, (pwm_period_ticks - 20));
    EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
    EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

    HWREGH(base1 + EPWM_O_AQCTLA) = 0;
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);

    EPWM_setDeadBandCounterClock(base1, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE);
    EPWM_setRisingEdgeDelayCount(base1, pwm_db_ticks_hs);
    EPWM_setFallingEdgeDelayCount(base1, pwm_db_ticks_ls);
    EPWM_setDeadBandDelayMode(base1, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(base1, EPWM_DB_FED, true);
    EPWM_setRisingEdgeDeadBandDelayInput(base1, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(base1, EPWM_DB_INPUT_EPWMA);
    EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);

    EPWM_disablePhaseShiftLoad(base1);
    EPWM_enableSyncOutPulseSource(base1, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);

    EPWM_setPeriodLoadMode(base2, EPWM_PERIOD_DIRECT_LOAD);
    EPWM_setTimeBasePeriod(base2, (pwm_period_ticks - 1));
    EPWM_setTimeBaseCounter(base2, 2);
    EPWM_setPhaseShift(base2, 2);
    EPWM_setTimeBaseCounterMode(base2, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_setClockPrescaler(base2, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    EPWM_setCounterCompareValue(base2, EPWM_COUNTER_COMPARE_A, 0);
    EPWM_setCounterCompareValue(base2, EPWM_COUNTER_COMPARE_B, 0);
    EPWM_setCounterCompareShadowLoadMode(base2, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
    EPWM_setCounterCompareShadowLoadMode(base2, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

    HWREGH(base2 + EPWM_O_AQCTLA) = 0;
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN);

    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN);

    EPWM_setActionQualifierT1TriggerSource(base2, EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT);

    XBAR_enableEPWMMux(XBAR_TRIP5, 0x00);
    XBAR_setEPWMMuxConfig(XBAR_TRIP5, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP5, XBAR_MUX00);

    EPWM_selectDigitalCompareTripInput(base2, EPWM_DC_TRIP_TRIPIN5, EPWM_DC_TYPE_DCAH);
    EPWM_setTripZoneDigitalCompareEventCondition(base2, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setDigitalCompareEventSource(base2, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);
    EPWM_setDigitalCompareEventSyncMode(base2, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_NOT_SYNCED);
    EPWM_enableTripZoneSignals(base2, EPWM_TZ_SIGNAL_DCAEVT2);
    EPWM_enableDigitalCompareBlankingWindow(base2);
    EPWM_setDigitalCompareFilterInput(base2, EPWM_DC_WINDOW_SOURCE_DCAEVT2);
    EPWM_setDigitalCompareBlankingEvent(base2, EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD);
    EPWM_setDigitalCompareWindowOffset(base2, pwm_period_ticks - 5);
    EPWM_setDigitalCompareWindowLength(base2, 12);

    EPWM_setTripZoneAdvAction(base2, EPWM_TZ_ADV_ACTION_EVENT_TZA_D, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(base2, EPWM_TZ_ADV_ACTION_EVENT_TZA_U, EPWM_TZ_ADV_ACTION_DISABLE);
    EPWM_setTripZoneAdvAction(base2, EPWM_TZ_ADV_ACTION_EVENT_TZB_U, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(base2, EPWM_TZ_ADV_ACTION_EVENT_TZB_D, EPWM_TZ_ADV_ACTION_DISABLE);
    EPWM_setTripZoneAction(base2, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_DISABLE);
    EPWM_setTripZoneAction(base2, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_DISABLE);
    EPWM_selectCycleByCycleTripZoneClearEvent(base2, EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);

    EPWM_clearTripZoneFlag(base1, (EPWM_TZ_INTERRUPT_OST | EPWM_TZ_INTERRUPT_DCAEVT2 | EPWM_TZ_SIGNAL_DCBEVT1));
    EPWM_clearTripZoneFlag(base2, (EPWM_TZ_INTERRUPT_OST | EPWM_TZ_INTERRUPT_DCAEVT2 | EPWM_TZ_SIGNAL_DCBEVT1));

    EPWM_setDeadBandCounterClock(base2, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE);
    EPWM_setRisingEdgeDelayCount(base2, pwm_db_ticks_hs);
    EPWM_setFallingEdgeDelayCount(base2, pwm_db_ticks_ls);
    EPWM_setDeadBandDelayMode(base2, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(base2, EPWM_DB_FED, true);
    EPWM_setRisingEdgeDeadBandDelayInput(base2, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(base2, EPWM_DB_INPUT_EPWMB);
    EPWM_setDeadBandDelayPolarity(base2, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(base2, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);

    EPWM_setSyncInPulseSource(base2, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    EPWM_enablePhaseShiftLoad(base2);
    EPWM_enableSyncOutPulseSource(base2, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);
    EPWM_setPhaseShift(base2, 2);
    EPWM_setCountModeAfterSync(base2, EPWM_COUNT_MODE_UP_AFTER_SYNC);

    EDIS;
}

We would like to request the slope compensation aspect as well and seek your guidance on calculating and applying the correct slope compensation value for the ramp.

Best regards

Thanks for sharing the configuration code.

On the CMPSS PCMC configuration, I believe you use CMPSS high comparator for this function like the ref design. The only thing I can notice is that you use the filter output to drive the PWM trip. This should be ok, this will filter noise in the transformer current signal, but the downside is that there will be a delay between the time the transformer current meets the comparator ramp, and when the CMPSS generates the trip output to the PWM. 

CMPSS_configOutputsHigh(PSFB_PCMC_OCP_CMPSS_BASE, CMPSS_TRIP_FILTER | CMPSS_TRIPOUT_FILTER);

You can try to change the PWM trip to come from the async comparator output instead like the code below to see if there is any difference in behavior. Note: you definitely want the TRIPOUT to come from the filter output. Otherwise, the CMPSS ramp will reset too quickly and the PWM trip will be too short for the PWM to latch properly.

CMPSS_configOutputsHigh(PSFB_PCMC_OCP_CMPSS_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_ASYNC_COMP))

The trip zone and action qualifier settings look ok too. 

I would suggest that you bring the CMPSS TRIPOUT signal to a GPIO pin using the output XBAR. With this signal you should be able to definitively tell when the CMPSS is generate the trip event to the PWM. With this info we can tell if any trips are missing during the error condition. 

Thank you for your comment.

Due to the Lunar New Year holidays, we couldn't check your response sooner.

We will review the two points you mentioned for further analysis, particularly regarding changing the settings to Async and visualizing the CMPSS TRIPOUT signal.

We have an additional query about the effect of noise in the VDDA signal.

For the DAC reference voltage, we have selected VDDA (3.3V) as its supply voltage.

    // Use VDDA as the reference for the DAC and set DAC value to
    //
    CMPSS_configDAC(PSFB_PCMC_OCP_CMPSS_BASE, CMPSS_DACREF_VDDA |       // DAC Value -> Cmpss negative input
                    CMPSS_DACVAL_PWMSYNC | CMPSS_DACSRC_RAMP);

<CMPSS from TMS320F280039C datasheet>

Do you think the presence of noise in VDDA could be contributing to this behavior?

Note: The VDDA is connected to pin 34 of TMS320F280039C DSP.

Best Regards

    // Use VDDA as the reference for the DAC and set DAC value to
    //
    CMPSS_configDAC(PSFB_PCMC_OCP_CMPSS_BASE, CMPSS_DACREF_VDDA |      
                    CMPSS_DACVAL_PWMSYNC | CMPSS_DACSRC_RAMP);

Yes, it is possible. Since VDDA is also used by the ADC, the ADC reading would also be affected. 

Hi, we checked two things

1. "change the PWM trip to come from the async comparator output instead" using

CMPSS_configOutputsHigh(PSFB_PCMC_OCP_CMPSS_BASE, (CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_ASYNC_COMP))

In the user manual, we found that bypassing the filter helps to avoid delay be 2 sysclks. (please see the snapshot below taken from the technical manual).

Results: It did not solved the issue and we still face short circuit issue.

2. "bring the CMPSS TRIPOUT signal to a GPIO pin using the output XBAR".

Result: No trip signals were missed before the Short Circuit.

Here are the waveforms:

<There is a delay of 400ns between the trip command from CMPSS and the turning off of the switch>

and just before the short circuit

The trip appeared before as normal, however, the current continued to increase causing short circuit protection operation.

Since we are still facing the same issue, I have following additional queries:

1. Can we use internal voltage regulator (reference) for DAC? If so then could you please share some document/tutorial for selecting internal voltage reference.

Will there be any drawbacks of using internal voltage?

Thank you

Hello,

I am working with Abdur.

I have one question.

See the isseued waveform, time is over 50% duty.

If Duty time is near the 50% duty, Is there a way to force PWM off?

Regards,

Sangmo Kim.

Hello,

I checked CMPSS TRIPOUT signal again.

Below waveform is measured when output load is fixed.

Output voltage is operating normal, than suddenly happened peak voltage.

When happened peak voltage, Icommand dose not change. 

And Main transformer current is increase. also MCU input Main transformer current increase too.

But There is no CMPSS TRIPOUT signal.

What do you think?

CH1 12Vmain

CH3 CMPSS TRIPOUT signal

CH4 MCU input Main transformer current

CH6 Main transformer current

CH8 Icommand

Regards,

Sangmo Kim.

Hi, Let me describe Sangmo's Comment in more detail.

This matter is extremely urgent and we would greatly appreciate a prompt response from TI in order to resolve this issue.

Below are more waveforms of the trip signals (CMPSS --> X-BAR Output --> GPIO (Trip Signal)).

The width of the trip signal gradually decreases and as the duty reaches near 50%, it is completely disappeared (Trip Pulse 3 is missed below).

<RED Waveform: Trip Pulses, Yellow: Tr Pri Current>

Pulse 1 width: 77.9ns.   

Pulse 2 width: 29.9ns 

This is unusual, and as can be seen, due to missing a trip signal, the ePWM modules does not turns off the PWM. And it is contineous, and the pattern repeats.

1. What could be the reason for this behaviour and how can we solve it?

2. For PCMC, how can we add some limit on duty (as the current is compared realtime with the reference). Is it possible to use some condition in the ePWM module. Like if some trip signal is missed, then don't wait, and turn off the PWM after some specified time.

Thank you

Abdur Rehman said:

1. What could be the reason for this behaviour and how can we solve it?

What scope channel is the CMPSS fault pulse trigger source? Does the scope have dual time base sampling or ability sample channel B after A trigger source? Reason being the horizontal timeline of samples may be misleading depending on how the scope triggering is set. Anyways inductor current (Tr Pri) may not diminish for some time after CMPSS trip event has triggered PWM action qualifier.

One thought reading tread: As inverter MOSFET heat >25°C (under sustained load) dead band area (D/S) decays. Hence, circuit may be having shoot through event and CMPSS trip clamps D/S short below protection diode Trr, So MOSFET is not destroyed, lucky. Perhaps increase dead band timing and or add some CMPSS hysteresis. Seemingly there is no PWM blanking delay for compensating spurious trip events due to load type and line voltage conditions.  

Apologies for late response. I want to try and address as many of your queries as possible.

Abdur Rehman said:

1. Can we use internal voltage regulator (reference) for DAC? If so then could you please share some document/tutorial for selecting internal voltage reference.

Will there be any drawbacks of using internal voltage?

No, reference voltage must be provided externally through VDDA or VDAC pin.

sangmo kim said:

If Duty time is near the 50% duty, Is there a way to force PWM off?

Abdur Rehman said:

2. For PCMC, how can we add some limit on duty (as the current is compared realtime with the reference). Is it possible to use some condition in the ePWM module. Like if some trip signal is missed, then don't wait, and turn off the PWM after some specified time.

Yes, of course. In a phase-shifted system, the CMPSS event will force the PWM output high or low depending on which half of the PWM cycle you are on (see waveform below). The PWM is further configured to set the PWM high or low using the PRD and ZRO events. In the event that the CMPSS trip does not come, the PRD and ZRO event will still ensure the PWM output goes to the right state & should ensure the duty cycle is not greater than 50%. I had checked this configuration in your PWM settings, but please double check to be sure.

It seems the basic problem is that the CMPSS is not generating a trip event. Let me think some more on this and I will provide further feedback. 

Abdur Rehman said:

Red waveform: Input current (I_Iinput​)

From Fig. 1, we observed that just before the short circuit, the pink gating signal fails to turn off earlier than the light green gating signal, as expected.

Seemingly HV current is monitored via FB resistor divider primary T1, low voltage +/- input signal to analog block CMPSS. If the DACVAL-L output was not inverted could explain why CMPSS does not produce CBC pulse to PWM2-A/B, thus duty cycle (green signal) driving output current upward to handle sudden DC load primary T2. If nothing changed T2 primary or secondary DC load (30 minutes into testing), if not dead band timing perhaps CMPSS configuration issue.

           /* Configure inverting input for internal COMPDAC(VDDA3v3) reference
             * and low comparator inverted OR-ASYNCH filter outputs  */
            CMPSS_configHighComparator(obj->cmpssHandle[cnt],
                        CMPSS_INSRC_DAC | CMPSS_OR_ASYNC_OUT_W_FILT);
         
            CMPSS_configLowComparator(obj->cmpssHandle[cnt],
                        CMPSS_INSRC_DAC | CMPSS_OR_ASYNC_OUT_W_FILT
                                        | CMPSS_INV_INVERTED)
                                        
            /*Set 3x hysteresis on comparator inputs */
            CMPSS_setHysteresis(obj->cmpssHandle[cnt], 3);

1. We are using Teledyne Lecroy (HDO8038) oscilloscope, and the setting seems to be ok for sampling. 

As we repeated the experiment several times, this phenomenon is occuring contineously as soon as we start the experiment, and its periodic in nature. So, we can conclude that it is not linked with temperature. We just captured a single instance in our above result. you can see the trip pulses generated by the CMPSS. Just before the missing trip, the pulse width gets weak and weak. Ultimately, it diminishes.

2. The MOSFET leg is not getting short (no shoot through) as the Tr Pri current is increasing, and showing signs like saturation.

3. I will adjust the deadband and CMPSS hysteresis and will update you later.

If you can think of any other solution, please let us know.

Thank you

Thank you for your comment.

Yes, the PWM is configured to set the PWM high or low using the PRD and ZRO events. 

and for the case of CMPSS trip miss, the PRD and ZRO event are still operating and ensures that the duty cycle remains 50%.

Here, you can see, that the trip turns off the switch and S

The problem is, due to missing trip signal from CMPSS, the transformer current continues to rise and ultimately, due to sub-harmonic oscillations, the core starts to show signs of saturation and Short circuit protection operates.

Is there any way to somehow set maximum limit on the duty? So, Due to missing trip from CMPSS, PWM turns off with max duty.

Thank you

Let me share a more clear experiment picture of our problem.

Ch8: (Orange) CMPSS Trip Pulse
Ch4: (Green) Sensed input Current used by DSP for PCMC

Ch6: (Blue) Trans Pri Current

Ch1: (yellow) Output voltage

Here, please see the orange pulses, and the green waveform (sensed input current).

After the fourth Orange Pulse from the left

   - The input current (green) does not fully go down to zero

   - The tr Ipri (blue) also reaches its final value due to almost full duty (50%)

For the subequent cycle, since the Iref is fixed, the converter should have stopped, as now the current started from a higher level than before. However, it continues to increase and it seems like the reference value is not crossed by the sensed current, and no pulse is generated.

Thanks

Based on the information provided, I believe the issue is that the CMPSS pulse is clearing too quickly for the PWM to properly latch the event. I don't see a waveform from you which shows clearly shows the relationship between MCU transformer current input, PWM output, CMPSS trip output, and icommand. Therefore, I cannot validate my suspicion conclusively.

For clarity, the CMPSS trip pulse length is indirectly controlled by the CMPSS digital filter. When the comparator goes high, i.e. when the MCU transformer current meets the DAC value, the digital filter will start registering 1s, and the CTRIPH to the PWMs will go high (assuming CTRIPH is coming from the async path). When the digital filter counts 1s >THRESH, it will set its output high. This will in turn reset the RAMP to its maximum value which will mean the DAC voltage is > transformer current, and the comparator output will go low, which in turn will cause CTRIPH to the PWM to go low. I understand this may a bit confusing, but if you study the CMPSS chapter in the MCU TRM it should become a little clearer.

Bottom line, the digital filter must be configured such that it holds the CTRIPH signal for at least 3 TBCLK PWM cycles.

"A minimum of 3*TBCLK low pulse width on TZn inputs is sufficient to trigger a fault condition on the ePWM module. If the pulse width is less than this, the trip condition cannot be latched by CBC or OST latches."

It is important to keep in mind the module clock frequencies here. The CMPSS digital filter operates at SYSCLK/CLKPRESCALE.

The PWM is operating at TBCLK.

I would suggest you review the clock divider settings in CMPSS and PWM. Then adjust the CMPSS digital filter to ensure the minimum 3 TBLK cycles required by the PWM. You can also bring out the ASYNC CMPSS trip to the GPIO so you can see exactly what the PWM is seeing and can further validate if the CMPSS is meeting the 3 PWM cycle requirement. 

sangmo kim said:

this phenomenon is occuring contineously as soon as we start the experiment, and its periodic in nature.

That is not what was initially posted being the issue.

Abdur Rehman said:

he converter experiences a short circuit after running for about 30 minutes under full-load operating conditions.

 Then not actually a short circuit and CMPSS current limiting is not fully regulating HV drive current CBC during perceived overload condition. Expecting CMPSS DACL output to ever operate during HV zero crossing negative over current event seems futile. Relative to how other forums configure CMPSS DACL output to detect zero crossing negative current events from DACH zero crossing positive events. Hence if AC input line disturbance during sine wave negative half cycle it will pass down through T1 primary and beyond.

  So current detection HV circuit into DACL has to monitor negative zero crossing power line events for CMPSS DACL output XBAR signal driving PWM2-A/B DACL trip H or L events. PWM DAC trip timing also and seemingly correlates with dead band generator, where PWMA drive is inverted to create PWMB drive and relative to AC current produce by zero crossing switched H bridge primary T2. PWM drives should be somewhat synchronous to AC line disturbance events, <=1µs CBC fault trips both PWMnA and PWMnB.

Genatco, this is a DC to DC application. There is no zero crossing events because there is no AC current. The transformer current does go through positive and negative cycles, but the current signal is rectified before it is delivered to the MCU. 

Hi Gus,

Right, do see DC-DC converter. Note TP3 (CS_HV) no electrolytic capacitor filtering HV pulse/s diving DC pulses below ground during surge condition flyback T1 with DC battery source derived AC line powered M1-M2. Anyway, odd part of above captures PWM1/2-A/B signal above scope captures (duty cycle) PWM-A not so much B reduced or inverted or visa-versa. Why did other arbitrary channels remain at 50% duty cycle if CMPSS configured analog MUX could drive 4 PWM DAC channels? Would it not be prudent to do a CBC current limit on all four PWM channels driving phase shifted zero switched Full Bridge? Why not CMPSS set to trip High, inverted output matching DCAL, DCBL multiple combination trips? Seemingly configuration below delays async trip events >50µs @20KHz next PWM switching cycle, deadband band generator suspected. Perhaps adding MOV across AC power line inputs M1 & M2 could reduce line transients. Suggest scope TP3 see what is going on in HV_FB during disturbance.

Note customer urgency, TIDI-2000 module is not to be resold and or used in any part of consumer devices. Example software provided as is, may require debugging and or modification to fine tune device operation to the satisfaction of the developer.   

XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX01_CMPSS1_CTRIPL);
XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX01);

EPWM_selectDigitalCompareTripInput(base1, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH);
EPWM_selectDigitalCompareTripInput(base2, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH);
EPWM_selectDigitalCompareTripInput(base3, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH);

EPWM_setTripZoneDigitalCompareEventCondition(base1, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);
EPWM_setTripZoneDigitalCompareEventCondition(base2, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);
EPWM_setTripZoneDigitalCompareEventCondition(base3, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);

Thank you for your comments and sorry for the late reply.

We are mainly checking via the Digital Filter path.

Here, you mean once the digital filter outputs high, it also resets the ramp generation at the same time (to its max value).

We tried both, path 1(async) and path 2(digital filter), and visualized CTRIPOUTH on oscilloscope.

For Digital Filter, we kept the prescaler to 0 (i.e., value 1) in order to minimize the delay caused by the filter. However, both cases resulted in skipping of a pulse.

What we have understood until now is:

--> The problem starts when the converter tries to stabilize after experiencing sub harmonic oscillations. During this time, the converter duty reaches 100%, and the CMPSS generates normal trip signal at the end of cycle. The Itr(pri) shows maximum power transfer operation. The DSP related issue occurs in the next cycle.

   Due to sub harmonic oscillation, the very next cycle should have terminated early (i.e., ramp reference and measured current should have intersected earlier). However, the CMPSS misses this trip, and the cycle terminates due to ePWM period zero. We are still trying to figure out why the CMPSS missed the trip in the very next cycle after the full duty cycle. 

<Blue: Itr(pri),  Orange: CTRIPOUTH (GPIO plot),   Green: CT output (before the DSP pin)

Is it possible to visualize the internal Ramp signal via oscilloscope? If possible, then can verify whether the ramp is causing this problem or not?

Is it possible to access it via DMC?

Any other thoughts to solve this issue?

Thank you, Regards

At first, we ran the converter for aging test, however, (30 minutes), and experienced short circuit.

As the time passed, we received more feedback/help from Mr. Gus and you, so we checked more in detail.

Once thing in particular was, well before the short circuit, the converter first experiences missing the pulses coming out on CTRIPOUTH (visualized via GPIO on oscilloscope). And this occurs frequently due to the presence of noise. With strong slope compensation, the problem becomes less frequent, however, missing of trip pulse does occur all the time.

Note: DACL (CMPSSL) is used for Over current protection, whereas DACH (CMPSSH) is used for current control.

We already tried increasing the deadtime, however this doesn't resovle the issue.

As pointed out by Gus, we are working on DC-DC converter, whereas the current at the input of FB is used for PCMC. 

Regards

Abdur Rehman said:

Note: DACL (CMPSSL) is used for Over current protection

  What is the DACL over current trip value (hal.h / x.c?) and why is not CBC regulating PWM2-A/B duty cycle, PWM1A/B are relative phase control via DACH? Seems you mainly suspect DACH, maybe ramp generator shown above. The one thing known to be true about PWM modules (any class) direct update of comparator registers versus shadow copy update can cause odd electrical issues during immediate update of dead band generators.

  How are the dead band generators updated, individual PWM-1/2 immediate, shadow or global? We noticed odd behavior via global update with shadow copy via x49c comparator A. Have you check the x39c MCU errata PDF, though x49c did not list any issues with comparator A/B updates shadow copied perfectly. Yet global updates of 3 PWM generators did not work so well contrary to older type PWM modules that did.

  One would think x39c dead band generator preforms better in complementary mode for separate and immediate comparator A updates. Seemingly OVC/FB(PCMC) for PWM1/2 should act independently, DACVAL-H versus DACVAL-L. during dead band cycle. The way dead band is configured, signal A inverts to make B both PWM generators,1&2. Perhaps are not acting independent during bizarre PWM cycle disruption. The inverted double low PWM2 with single pulse (blue) in the middle of two lows should reflect near opposite signal trace in PWM1 (green) though PWM2-B (inverted) does not seem to reflect PWM2-A phase shift (green B?) near the end of the CBC pulse cycle. Combined dead band generator can cause unexpected PWM drive signals relative PWM action qualifies, MDAC triggering via analog MUX inputs from CMPSS DAC-H/L asynchronous trip events.

Have you tested even added CPMSS Hysteresis code?

We plotted DACHVALA by first accessing it via DMA and then using DAC to view it on oscilloscope.

Waveforms: 
CH6:: Purple : Itr(pri)

CH3: Cyan : DACHVALA register values

The ramp resets, however, the countdown for this register does not starts. 
It should have start countdown. Any suggestions?

Abdur Rehman said:

CH3: Cyan : DACHVALA register values

Abdur,

What came first, possible line transient HV_FB (TP3) or extended high ramp pulse noninverting input (A)?

You have not scope captured TP3 during the ramp pulse time. Are you located in an industrial zone? Someone running Tig/Arc welder on the same AC power line transformer? Note the circuit HV_FB, HV_FLT monitor signals zero EMI protection, DNP R24, R49, R26. why DNP? Perhaps random EMI riding on HV_FB input (TP3)? Note HV_FLT / HV_FB are tied together

Could reduce value C23 100pF monitor TP3 and note pulse time change via DAC ramp scope capture. Seems you suspect hardware software issue. Yet not giving any details of AC power line conditions in the building or capturing AC power line at the same time the electrical disturbance occurs.  

I'm actually impressed with the clever use of the DMA and DAC to view the ramp status!

Here is the description of the ramp operation:

The ramp generator is enabled by setting DACSOURCE = 1. When DACSOURCE = 1 is selected, the value of RAMPSTS is loaded from RAMPMAXREFS and the register remains static until the selected EPWMSYNCPER signal is received. After receiving the selected EPWMSYNCPER signal, the value of RAMPDECVALA is subtracted from RAMPSTS on every subsequent SYSCLK cycle.

Looking at your CMPSS configuration, something doesn't look right. You are writing "8" to RAMPSOURCE, which is not valid since the device only has 8 PWM modules. A value of "8" indicates EPWM9 which does not exist. Can you double check this?

    EALLOW;
    HWREGH(PSFB_PCMC_OCP_CMPSS_BASE + CMPSS_O_COMPDACCTL) =
        (HWREGH(PSFB_PCMC_OCP_CMPSS_BASE + CMPSS_O_COMPDACCTL) &
         ~(CMPSS_COMPDACCTL_RAMPSOURCE_M)) | (8);
    EDIS;

We already shared the HV_FB (TP3) waveform in our earlier reply. Let me share here as well.

Here green signal is the sensed current at point TP3 (HV_FB in the reference design note).

As can be observed, there is no noise in TP3 (sensed primary side current), and the trip pulse is still missing. Please note that we are doing the tests in a laboratory environment, and the converter has two stages:   AC-DC  and DC-DC. Since, there is a DC-link, so we expect the input to the DC-DC stage (PSFB) to be stiff and not changing. and since no noise can be observed in the TP3 (green waveform), we can say the 1st stage is not interfering here.

We already tried fully removing this RC filter (R32, 1kohm and C23 330pF) to remove the delay in TP3. However, the missing pulse still occurs.

With RC filter having (1k, 330pF) values, filter's cutoff frequency (fc) is 482kHz. With your suggested (1k, 100pF), fc is 1500kHz, means little to no filtering.

However, we suspect the problem is linked with CMPSS settings. We will can capture TP3 and Trip pules signal again, but it seems that we already know how it will look as we already have the waveforms above.

Thank you

Here, 8 (i.e., 0000 1000) is the correct value for selecting ePWM 5 as the sync source. To select ePWM 9, we must use 18 (i.e., 0001 0010).

The first LSB is ignored, as it is meant for the DACSource and must be 0. The next four bits determine the Ramp Source. In case of ePWM 5, it is 0100 (i.e., 4), which corresponds to ePWM 5.

After carefully reviewing the waveform (and the DACHVALA values from the ramp plot), we suspect that the Trip Pulse and the ePWM sync are occurring simultaneously, btw, is it possible??

As a result, the ramp generator resets, but however, it seems to ignore the ePWM sync value for starting the countdown process.

What are your thoughts on this?

Abdur Rehman said:

With RC filter having (1k, 330pF) values, filter's cutoff frequency (fc) is 482kHz. With your suggested (1k, 100pF), fc is 1500kHz, means little to no filtering.

Yet TI circuit HVFB you posted is not the one shown TIDM-02000; Schematic has full wave bridge rectifier primary side. Secondly reducing 330pF will increase HVFB pulse response window, shorten signal falling edge. So, it ignores random periodic spikes your scope will indeed fail to capture in continuous trigger mode.

That was primary reason for suggesting circuit change but you can do simple transient detection test on TP3. Set scope channel single trigger mode, negative (-200Mv to -500Mv) just to be sure a very rapid transient pulse is not escaping continues trigger captures. Some if not most transients can be in the megahertz range. We add inline ferrite bead chips being very effective arresting high frequency ringing transients riding on DC signals. 

BTW: The captures being posted indicate more near the end of the event trail that caused the first CBC trip event pulse to linger several PWM cycles. Why not also focus on what caused the very first trip event pulse, not so much the missing pulse. The only other place a transient might occur in the secondary Battery T2 circuit. Seeming you can also change one or the other current trips from CBC to One Shot to isolate what side of the circuit caused the first trip event.    

Abdur Rehman said:

The first LSB is ignored, as it is meant for the DACSource and must be 0. The next four bits determine the Ramp Source. In case of ePWM 5, it is 0100 (i.e., 4), which corresponds to ePWM 5.

Yes, you are absolutely right. I misread this.

Abdur Rehman said:

After carefully reviewing the waveform (and the DACHVALA values from the ramp plot), we suspect that the Trip Pulse and the ePWM sync are occurring simultaneously, btw, is it possible??

It is possible you are hitting a corner case here where the COMPHSTS (ramp reset) is coming after the EPWMSYNCPER signal, causing the ramp to reset and stop until the *next* EPWMSYNCPER pulse. I'll have to check with our CMPSS experts to see if there is a way around this. 

I discussed with a colleague. It is conceivable that you are hitting the corner condition where COMPHSTS is coming after the EPWMSYNCPER signal as shown in the diagram below. 

Gus Martinez said:

I discussed with a colleague. It is conceivable that you are hitting the corner condition where COMPHSTS is coming after the EPWMSYNCPER signal as shown in the diagram below. 

 Are the CMPSS (input / outputs) Asynchronous events to ePWM Synchronous PRD clock, yes. Seemingly the HV_FB fault trigger OVC trip point is a hardwired RC time constant? One might imagine no CBC trigger pules get to ePWM_DAC when the AC side current peaks remain below a preset RMS peak?

HV_FB signal could be of varying width, edge events only occur relative to actual OVC faults. So, the CMPSS output pulse width trips CBC the MDAC only when the edge event (offset) is of certain width relative ePWM pulse width. Otherwise MDAC ignores CMPSS pulses with shorter edge events due to blanking in the ePWM duty cycle pulse width.

x49c MCU class

/* Set CMPSS2 Blanking of LATCHCLR0-ePWM1 */
CMPSS_configBlanking(CMPSS2_BASE, 1);

/* Set CMPSS4 Blanking of LATCHCLR1-ePWM2 */
CMPSS_configBlanking(CMPSS4_BASE, 2);

/* Enable CMPSSx Blanking of LATCHCLR */
CMPSS_enableBlanking(obj->cmpssHandle[cnt]);

// ePWM Fault Edge Balnking:

    /* Set the DC-1A/1B BLANKWDW to sync PWM periods
     * TRM: 18.1.4.2 PG.1878 Figures 18-54/55 */
    EPWM_setDigitalCompareBlankingEvent(obj->pwmHandle[cnt], EPWM_DC_WINDOW_START_TBCTR_ZERO);
															//EPWM_DC_WINDOW_START_TBCTR_PERIOD

    /* Set DCx offset between window start pulse and blanking
     * window in number TBCLK's(10ns), offset=10µs  */
    EPWM_setDigitalCompareWindowOffset(obj->pwmHandle[cnt], 1000);

    /* Set DCx filter blanking window width TBCLK(10ns), width=5µs */
    EPWM_setDigitalCompareWindowLength(obj->pwmHandle[cnt], 500);

    /* Enable the DCx Blanking window */
    EPWM_enableDigitalCompareBlankingWindow(obj->pwmHandle[cnt]);

    /* Sset the Edge filter mode for Rise/Fall */
    EPWM_setDigitalCompareEdgeFilterMode(obj->pwmHandle[cnt], EPWM_DC_EDGEFILT_MODE_RISING);

    /* Set DC filter 1 edge count required to trigger DC events */
    EPWM_setDigitalCompareEdgeFilterEdgeCount(obj->pwmHandle[cnt], EPWM_DC_EDGEFILT_EDGECNT_1);

    /* Enable the DC edge filter */
    EPWM_enableDigitalCompareEdgeFilter(obj->pwmHandle[cnt]);

Point to consider, AC line voltage EURO 200V 50Hz versus USA 118V 60Hz.

Seemingly the OVC filter circuit (HV_FB) for EURO DC-DC might have few differences over US filter design?

Yes, the input and output of the analog comparator in the CMPSS is wholly dependent on the current in the transformer. At high phase shift angle, i.e. when the load is high, it is possible for the transformer current to mee the CMPSS ramp close to the end of the CMPSS period, which would coincide with the PWM sync pulse.

Hello,

Thank you for your comment.

I will find to can measure ePWM5.

I heard about the corner case from Steve at TI Korea.

When I measured the waveform, I realized that the RAMP reset could be after the RAMP sync.

I am going to modify and test the ePWM5 with RAMP sync behavior.

   * pwm_period_ticks-5 ---> 1

EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_C,
                                pwm_period_ticks - 5);
---->
EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_C,
                                1);

I think I can make RAMP sync always happen after reset if I set it like below, please let me know what you think.

void PSFB_HAL_setupAdcOvrSamplPWM(uint32_t base1, uint16_t pwm_period_ticks)
{
    EALLOW;

    EPWM_setPeriodLoadMode(base1, EPWM_PERIOD_DIRECT_LOAD);
    EPWM_setTimeBasePeriod(base1, pwm_period_ticks - 1);
    EPWM_setTimeBaseCounter(base1, 2);
    EPWM_setPhaseShift(base1, 2);
    EPWM_setTimeBaseCounterMode(base1, EPWM_COUNTER_MODE_UP);
    EPWM_setClockPrescaler(base1, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    EPWM_enablePhaseShiftLoad(base1);

    HRPWM_setSyncPulseSource(base1, HRPWM_PWMSYNC_SOURCE_COMPC_UP);
    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_C,
                                1);

    EPWM_setSyncInPulseSource(base1, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); // 250210
    EDIS;
}

Thanks.

Before modifying the PWM sync pulse behavior, I would suggest capturing this pulse in the scope while the error happens. Need to be sure this is the issue before implementing any fix for it. 

Perhaps keep in mind the CMPSSn (Gus mentioned above) has mandated conditions to set CBC latch state, 3 clock cycles. Seemingly SYSCLK being the peripheral clock source CMPSSn and NOT TBPRD clock source of ePWM modules. Again, T1 primary signal may vary asynchronously relative to SYSCLK by several hundred cycles, EURO 200VAC 50Hz supply voltage. Guss please correct me if this text does not apply to the issue in this thread. Setting up edge event delay offset of several microseconds any period might avoid the near SyncI / SyncPER edge MISSING pulse seemingly showing up in the very next PWM period. 

18.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis When using the CMPSS to trip the ePWM on a cycle-by-cycle basis, steps should be taken to prevent an asserted comparator trip state in one PWM cycle from extending into the following cycle. The CMPSS can be used to signal a trip condition to the downstream ePWM modules. For applications like peak current mode control, only one trip event per PWM cycle is expected. Under certain conditions, it is possible for a sustained or late trip event (arriving near the end of a PWM cycle) to carry over into the next PWM cycle if precautions are not taken.

If either the CMPSS Digital Filter or the ePWM Digital Compare (DC) submodule is configured to qualify the comparator trip signal, “N” number of clock cycles of qualification will be introduced before the ePWM trip logic can respond to logic changes of the trip signal. Once an ePWM trip condition is qualified, the trip condition will remain active for N clock cycles after the comparator trip signal has de-asserted. If a qualified comparator trip signal remains asserted within N clock cycles prior to the end of a PWM cycle, the trip condition will not be cleared until after the following PWM cycle has started. Thus, the new PWM cycle will detect a trip condition as soon as it begins.

To avoid this undesired trip condition, the user application should take steps to ensure that the qualified trip signal seen by the ePWM trip logic is deasserted prior to the end of each PWM cycle. This can be accomplished through various methods: • Design the system such that a comparator trip will not be asserted within N clock cycles prior to the end of the PWM cycle. • Activate blanking of the comparator trip signal via the ePWM event filter at least two clock cycles prior to the PWMSYNCPER signal and continue blanking for at least N clock cycles into the next PWM cycle. • If the CMPSS COMPxLATCH path is used, clear the COMPxLATCH at least N clock cycles prior to the end of the PWM cycle. The latch can be cleared by software (via COMPSTSCLR) or by generating an early PWMSYNCPER signal. The ePWM modules on this device include the ability to generate PWMSYNCPER upon a CMPC or CMPD match (via HRPCTL) for arbitrary PWMSYNCPER placement within the PWM cycle