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TMS320F28P650DK: Use of GPREG with CLB ASYNC mode

Mattia Bacci
Prodigy 140 points

Part Number: TMS320F28P650DK

Tool/software:

Hi, 

i have set up the CLB to run in ASYNC mode at 100MHz from the AUXPLL clock, while my CPU is running at 200MHz.

From the TRM is not clear if in this case the CLB_INPUT_FILTER.PIPE[n] should be set.

Thanks.

  • 0
    TI__Mastermind 28580 points

    Hello,

    The pipeline mode should only be set when the CLB is running at frequencies higher than 100 Mhz, so you won't need to enable it in this case.

  • 0 in reply to Luke Jones
    Prodigy 140 points

    Hi,

    that is clear. But the "Pipeline mode" is the same of CLB_INPUT_FILTER.PIPE[n]? From this part it seems that they are not the same.

    Pipeline mode needs to be enable to use CLB_INPUT_FILTER.PIPE[n]?

    If pipeline mode is disabled and i set CLB_INPUT_FILTER.PIPE[n] = 1, what will happen?

  • +1 in reply to Mattia Bacci
    TI__Mastermind 28580 points

    The CLB_LOAD_EN.PIPELINE_EN bit is just for the HLC and counters. This should also be enabled if the CLB clock is running above 100 Mhz.

    Setting CLB_INPUT_FILTER.PIPE[n] will add a delay to the input and is not recommended if the CLB clock is <= 100 Mhz, however the CLB should still function as normal if there are no strict timing requirements between multiple inputs of the CLB.

    Thank you,

    Luke