TMS320F28235: Clock jitter for XCLKIN

Oba

Tool/software:

Hello,

My customer is designing their protoytpe with TMS320F28235.
Then they would like to check if the below input clock spec is no problem because it is a llittle bit worse specification than one they used before.
Is this jitter spec acceptable for XCLKIN input?

Period Jitter (Peak to Peak):344.1ps
RMS Jitter (1-sigma):31.2ps
Random Jitter (RJ) :66.9ps

Regards,
Oba

over 1 year ago

0 Matt Kukucka over 1 year ago

TI__Genius 15440 points

Hi Oba,

Parameters such as frequency and jitter tolerance are determined by your application (as allowed by your ePWM or ADC sample, for example), not by the oscillator. In other words, you need to determine how much tolerance and jitter your application can tolerate. This does not impact the oscillator itself.

Best,

Matt

0 Oba over 1 year ago in reply to Matt Kukucka

TI__Genius 17705 points

Hello Matt,

Thanks for your reply.
Doesn't it also impact PLL stability?

Regards,
Satoshi Obata

0 Matt Kukucka over 1 year ago in reply to Oba

TI__Genius 15440 points

Hi Oba,

Yes, you are correct. The jitter for the PLL will be the same as that of the external crystal used. Therefore, you have to determine if your application can tolerate the jitter that will propagate through the PLL from the input clock source.

Best,

Matt

0 Oba over 1 year ago in reply to Matt Kukucka

TI__Genius 17705 points

Hello Matt,

Thanks for your reply.
My concern is just PLL stability meaning if it stably stays "lock" condition, not jitter on PLL output.
It is no problem, isn't it?

Regards
Satoshi Obata

0 Matt Kukucka over 1 year ago in reply to Oba

TI__Genius 15440 points

Hi,

No, I do not see how that will be an issue.

Best,

Matt

+1 Matt Kukucka over 1 year ago in reply to Matt Kukucka

TI__Genius 15440 points

I will assume that this issue is resolved and close the thread, as its been several weeks without a response. Please open a new thread if that's not the case.

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TMS320F28235: Clock jitter for XCLKIN