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TMS320F28P650DK: CLB clock tree is not represented correctly

Mattia Bacci
Prodigy 110 points
Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi,

in the TRM under the clocking section the CLB clock tree is reported as follows:

In the CLB section is reported like this:

And in sysconfig like this:

also changing this values in sysconfig(CLBCLKDIV & TILECLKDIV) does not generate any code. So what is reported in sysconfig is clearly wrong.

Since that they are all different from each other, which of the three is the correct one?

  • 0
    TI__Mastermind 27850 points

    Hi Mattia,

    As far as the CLB register and CLB tile clocks are concerned, all three diagrams are the same even though they appear to be different at first glance. Please point out how the diagrams are functionally different from each other. The EPWMCLK path is not shown in the clocktree tool as the CLB module in sysconfig is responsible for selecting the clock source that is synchronized to EPWMCLK / SYSCLK.

    From testing on my side I see the .syscfg file is modified when I modify the clocktree GUI, however clocktree.h is not modified. Reassigning this thread to the clocktree tool expert to investigate this.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 110 points

    Hi,

    they are actually not the same at all,

    1. Under the clocking section (first picture) the EPWCLKDIV divider is before of both the TILE clock and the Register clock.
    2. In the CLB section (second picture) the EPWCLKDIV is only before of the TILE clock.
    3. In sysconfig the source of the CLBCLKDIV is RAWCLK, but in the other pictures is AUXPLL. 

    Also please note that the is no way in sysconfig to select between SYNC mode and ASYNC (so there is no option to choose the EPWCLKDIV path or the SYSCLK path).

    I have done this choice by code but sincerely i think that this clock selection is quite trivial seen that the sysconfig tool:

    1. Is representing the CLK tree wrong.
    2. Do not give the option to select the SYNC or ASYNC mode.
    3. Even if the representation is wrong changing the values in sysconfig clk tree for CLBCLKDIV & TILECLKDIV has no effect.

  • 0 in reply to Mattia Bacci
    TI__Genius 13605 points

    Hi Mattia,

    2nd Diagram in CLB section is accurate.

    Taking the feedback of Clocktree tool, we will make sure the representation is accurate from clock tree view in the next release
    The configurations better stay in CLB sysconfig section

    Thanks

  • 0 in reply to Prarthan Bhatt
    Prodigy 110 points

    Ok, thanks

    So if the 2nd Diagram in CLB section is accurate does this mean that the CLB Register Clock can reach 200MHz? This is not reported anywhere in the TRM or datasheet.

  • +1 in reply to Mattia Bacci
    TI__Genius 13605 points

    Hi Mattia,

    Yes Register clock can be Sysclk.

    Are you seeing any issue functionally wrt to CLB clock ? Register clock doesn't mater for users, only Tile clock should be considered based on the use case.

    Reassigning internally to CLB expert for further queries you may have.

    Thanks

  • 0 in reply to Prarthan Bhatt
    Prodigy 110 points

    Hi,

    no issue, its just to be sure.

    Since on the CLB section is reported that the maximum frequency can be 150MHz, by setting the CLB Register Clock to SYSCLK it will reach 200MHz. In general i think that the explanation on this part should be more clear. Also the fact that the CLB diagram in the clocking section of TRM is different causes even more confusion.