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TMS320F28P650DK: Sysconfig adding trip zone code to digital compare

Daniel Brown
Prodigy 145 points
Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

The generated code in board.c adds lines to configure trip zone when the sysconfig is only configured for digital compare and events.

Since my outputs are not correct, I am thinking this is an error.  

Sysconfig:

epwm9.epwmTimebase_hsClockDiv = "EPWM_HSCLOCK_DIVIDER_1";
epwm9.epwmTimebase_phaseEnable = true;
epwm9.$name = "pwmG9";
epwm9.epwmDeadband_enableRED = true;
epwm9.epwmDeadband_enableFED = true;
epwm9.epwmDigitalCompare_EPWM_TZ_DC_OUTPUT_A1 = "EPWM_TZ_EVENT_DCXH_HIGH";
epwm9.epwmActionQualifier_t2Source = "EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2";
epwm9.epwmDigitalCompare_EPWM_TZ_DC_OUTPUT_A2 = "EPWM_TZ_EVENT_DCXH_LOW";
epwm9.epwmDigitalCompare_EPWM_DC_MODULE_A_EPWM_DC_EVENT_1_latchMode = "EPWM_DC_CBC_LATCH_ENABLED";
epwm9.epwmDigitalCompare_EPWM_DC_MODULE_A_EPWM_DC_EVENT_2_latchMode = "EPWM_DC_CBC_LATCH_ENABLED";
epwm9.epwmTimebase_counterMode = "EPWM_COUNTER_MODE_UP_DOWN";
epwm9.epwmTimebase_period = 1000;
epwm9.epwmTimebase_counterModeAfterSync = "EPWM_COUNT_MODE_UP_AFTER_SYNC";
epwm9.epwmTimebase_phaseShift = 2;
epwm9.epwmDigitalCompare_EPWM_DC_MODULE_A_EPWM_DC_EVENT_1_latchClearEvent = "EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD";
epwm9.epwm.$assign = "EPWM11";
epwm9.epwm.epwm_aPin.$assign = "GPIO20";
epwm9.epwm.epwm_bPin.$assign = "GPIO21";

board.c

EPWM_setClockPrescaler(pwmG9_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
EPWM_setTimeBasePeriod(pwmG9_BASE, 1000);
EPWM_setTimeBaseCounter(pwmG9_BASE, 0);
EPWM_setTimeBaseCounterMode(pwmG9_BASE, EPWM_COUNTER_MODE_UP_DOWN);
EPWM_setCountModeAfterSync(pwmG9_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
EPWM_enablePhaseShiftLoad(pwmG9_BASE);
EPWM_setPhaseShift(pwmG9_BASE, 2);
EPWM_setCounterCompareValue(pwmG9_BASE, EPWM_COUNTER_COMPARE_A, 0);
EPWM_setCounterCompareShadowLoadMode(pwmG9_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setCounterCompareValue(pwmG9_BASE, EPWM_COUNTER_COMPARE_B, 0);
EPWM_setCounterCompareShadowLoadMode(pwmG9_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setActionQualifierT2TriggerSource(pwmG9_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
EPWM_setActionQualifierAction(pwmG9_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
EPWM_setDeadBandDelayMode(pwmG9_BASE, EPWM_DB_RED, true);
EPWM_setRisingEdgeDelayCountShadowLoadMode(pwmG9_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);
EPWM_disableRisingEdgeDelayCountShadowLoadMode(pwmG9_BASE);
EPWM_setDeadBandDelayMode(pwmG9_BASE, EPWM_DB_FED, true);
EPWM_setFallingEdgeDelayCountShadowLoadMode(pwmG9_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);
EPWM_disableFallingEdgeDelayCountShadowLoadMode(pwmG9_BASE);
EPWM_setTripZoneDigitalCompareEventCondition(pwmG9_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);
EPWM_setTripZoneDigitalCompareEventCondition(pwmG9_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_LOW);
EPWM_setDigitalCompareCBCLatchMode(pwmG9_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_ENABLED);
EPWM_selectDigitalCompareCBCLatchClearEvent(pwmG9_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD);
EPWM_setDigitalCompareCBCLatchMode(pwmG9_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_ENABLED);

  • 0
    Prodigy 145 points

    Trying to understand this more.  So maybe that is necessary. 

    Is there anything else that would cause my gate A to stay low while the gate B is happily reacting to the events?  That's my core problem.

    I even tried setting AQCTL to ignore T1 and T2 and gate A still stays low. 

  • 0 in reply to Daniel Brown
    Prodigy 145 points

    I discovered that if I want to use the Digital Compare events for T1 and T2 (so it will use deadband) but not as Trip Zone events, I need to go into Sysconfig and change from a High Impedance response to a Disable Action.