TMS320F28388D: EINT and Nesting

Hi Dorion,

By default, the CPU will service each interrupt to completion without breaking out of an ISR even if a higher priority interrupt gets flagged during its execution. Once the CPU finishes executing an ISR, it will then service the highest priority interrupt that is both flagged and enabled. The links you have mentioned give a solution for two different scenarios:

• Simple Nesting (Highest priority interrupts will be branched to no matter if the CPU is already servicing another interrupt)
  • Case 1: All interrupts are in different groups & priority from ePIE is good
    • In highest priority ISR
      • no additional code needed
    • In lowest priority ISR
      
      • EINT
      • ISR application execution
      • DINT
    • In medium priority ISRs (not highest or lowest priority)
      • clear all IERs in all lower priority groups
      • EINT
      • ISR application execution
      • DINT
  • Case 2: Two (or more) interrupts are from same group
    • In highest priority ISR
      • No additional code needed 
    • In lower priority ISRs of two interrupts within same group
      • Re-enable IER for group
      • Clear ACK for the group
      • wait 1 cycle (NOP)
      • EINT
      • ISR application execution
      • DINT
    • For extra protection (not always needed):
      • Clear the PIEIER each time to avoid spurious interrupting from the same group (ex. second interrupt of same ISR comes in during execution, and you want to avoid nesting and going into the second one before completing the first one)
• Changing Priority (Nesting to change priority in ePIE) - use the masks from the sw_prioritization_isr_levels.h
  • All interrupts being used are in different groups
    • In highest priority ISR
      • No additional code needed 
    • In all lower priority ISRs:
      • Enable IER of all higher priority interrupts
      • Clear ACK of current group
      • wait 1 cycle (NOP)
      • EINT
      • ISR application execution
      • DINT
  • 2 (or more) interrupts are from the same group
    • In highest priority ISR
      • No additional code needed  
    • In lower priority ISRs from a unique group
      • Enable IER of all higher priority interrupts
      • Clear ACK of current group
      • wait 1 cycle (NOP)
      • EINT
      • ISR application execution
      • DINT
    • In lower priority ISRs of two interrupts within same group
      • Save PIEIER of current ISR
      • Enable IER of all higher priority interrupts <- use masks from the header file for this
      • Enable PIEIER of all higher priority interrupts in same group <- use masks from the header file for this
      • Clear ACK of current group
      • wait 1 cycle (NOP)
      • EINT
      • ISR application execution
      • DINT
      • Restore PIEIER for current group

I am planning on updating the link you have mentioned with the information above and examples of each case. Please let me know if anything about it is unclear.

Best Regards,

Delaney

To answer your questions specifically:

Dorion Carr said:

Can a higher priority ISR, interrupt a lower priority if you are currently in the lower priority ISR handler?

1. Can this happen if they are in the same PIE group?

No, in normal operation this would never happen. It is possible to enable this for any combination of interrupts though (see Simple Nesting above)

Dorion Carr said:

Can this happen if they are NOT in the same PIE group?

Not in normal operation, however it is also possible. This would require just an EINT in the lower priority ISR.

Dorion Carr said:

Can this only happen if you do an EINT at the beginning of the lower priority ISR?

The EINT would be required, yes. If trying to nest an interrupt in the same group, modifications to the IER (and PIEIER optionally) and ack would also be needed. You would want to do these in the same order shown as in the example code.

Dorion Carr said:

With EINT done at the beginning of the ISR handler can a lower ISR interrupt the higher priority?

Yes, if the interrupt of a higher priority is in a different ePIE group.

Dorion Carr said:

How can a higher priority ISR interrupt a lower priority ISR in the same PIE group?

1. What masking do we use or does it just happen automatically.

You would need to do all of the following:

• Re-enable IER for group
• Clear ACK for the group
• wait 1 cycle (NOP)
• EINT

No need to use the masks. Modifying the PIEIER would be optional. Technically, the PIEIER for the higher priority interrupt would already be enabled when inside the lower priority ISR. You could just disable the PIEIER of the current group if you wanted to avoid spurious interrupts.

Dorion Carr said:

Regarding nesting:

1. If you have 2 ISRs not in the same PIE Group but you do an EINT at the beginning of the ISR handler can a lower priority ISR interrupt the higher priority? And vice-versa?

This case is why you would not want to add EINT to the higher priority ISR, just the lower (or all lower ISRs). That way only the higher priority ISR can nest the lower priority ISR and not vice versa. Theoretically if you added EINT to the higher priority ISR and a lower priority interrupt came in during execution, it would nest it yes.

Please upvote any responses that were helpful for you 

Best Regards,

Delaney

Hi Dorion,

I apologize for the delay. You are correct, adding just EINT could cause lower priority interrupts to nest inside. You need to modify the IER in the ISRs as well for all but the lowest priority ISR. So, for example, you can do the following in this case:

INT 1.3 (highest priority) - regular ISR

INT 2.1 - Clear IER for group 4 and group 7, then EINT

INT 4.2 - Clear IER for group 7, then EINT

INT 7.5 (lowest priority) - just add EINT

Best Regards,

Delaney