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TMS320F28375D: Help with phase shifted PWM.

Murali Manohar
Intellectual 320 points
Part Number: TMS320F28375D

Tool/software:

I am trying to generate 4 PWM signals. The PWM modules available to me are ePWM8, ePWM9, ePWM10, and ePEM11. I am trying to keep ePWM8 as the master and the other PWMs will be shifted from the master by 90°,180°, and 270° respectively. I am getting the required phase shift in ePWM9, but ePWM10 and ePWM11 shows the same signal as ePWM8. Should I configure ePWM7 so that the sync chain works properly? Since I have the 100 pin configuration, the pins for ePWM7 are used for some other function. I am attaching the configuration I am using along with the query. 

EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm8Regs.TBPRD = EPWM_TIMER_TBPRD;       // Set timer period
EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down
EPwm8Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm8Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;	// Enable sync
EPwm8Regs.TBCTR = 0x0000;                  // Clear counter
EPwm8Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading

EPwm8Regs.AQCTLA.bit.CAU = AQ_SET;      	// Set PWM8A on Zero
EPwm8Regs.AQCTLA.bit.CAD = AQ_CLEAR;    	// Clear PWM8A on event A, up count

EPwm8Regs.AQCTLB.bit.CBU = AQ_SET;     		// Set PWM8B on Zero
EPwm8Regs.AQCTLB.bit.CBD = AQ_CLEAR;    	// Clear PWM8B on event B, up count


EPwm8Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;    // Select INT on Period event
EPwm8Regs.ETSEL.bit.INTEN = 1;              // Enable INT
EPwm8Regs.ETPS.bit.INTPRD = ET_1ST;      	// Generate INT on First event

EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm8Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm8Regs.DBRED.bit.DBRED = EPWM_DB;
EPwm8Regs.DBFED.bit.DBFED = EPWM_DB;

EPwm9Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
EPwm9Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm9Regs.TBPRD = EPWM_TIMER_TBPRD;       // Set timer period
EPwm9Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down
EPwm9Regs.TBCTL.bit.PHSEN = TB_ENABLE;    // Enable phase loading
EPwm9Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm9Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	// Enable sync
EPwm9Regs.TBCTL.bit.PHSDIR = TB_DOWN;
EPwm9Regs.TBPHS.bit.TBPHS = EPWM_TIMER_TBPRD/2;        // Phase is 90

EPwm9Regs.AQCTLA.bit.CAU = AQ_SET;      	// Set PWM8A on Zero
EPwm9Regs.AQCTLA.bit.CAD = AQ_CLEAR;    	// Clear PWM8A on event A, up count

EPwm9Regs.AQCTLB.bit.CBU = AQ_SET;     // Set PWM8B on Zero
EPwm9Regs.AQCTLB.bit.CBD = AQ_CLEAR;    	// Clear PWM8B on event B, up count

EPwm9Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Period event
EPwm9Regs.ETSEL.bit.INTEN = 1;                // Enable INT
EPwm9Regs.ETPS.bit.INTPRD = ET_1ST;      // Generate INT on First event

EPwm9Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm9Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm9Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm9Regs.DBRED.bit.DBRED = EPWM_DB;
EPwm9Regs.DBFED.bit.DBFED = EPWM_DB;

EPwm10Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
EPwm10Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm10Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down
EPwm10Regs.TBCTL.bit.PHSEN = TB_ENABLE;    // Enable phase loading
EPwm10Regs.TBCTL.bit.PHSDIR = TB_DOWN;
EPwm10Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm10Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	// Enable sync
EPwm10Regs.TBPRD = EPWM_TIMER_TBPRD;       // Set timer period
EPwm10Regs.TBPHS.bit.TBPHS = EPWM_TIMER_TBPRD;        // Phase is 180

EPwm10Regs.AQCTLA.bit.CAU = AQ_SET;      	// Set PWM8A on Zero
EPwm10Regs.AQCTLA.bit.CAD = AQ_CLEAR;    	// Clear PWM8A on event A, up count

EPwm10Regs.AQCTLB.bit.CBU = AQ_SET;     // Set PWM8B on Zero
EPwm10Regs.AQCTLB.bit.CBD = AQ_CLEAR;    	// Clear PWM8B on event B, up count

EPwm10Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Period event
EPwm10Regs.ETSEL.bit.INTEN = 1;                // Enable INT
EPwm10Regs.ETPS.bit.INTPRD = ET_1ST;      // Generate INT on First event

EPwm10Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm10Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm10Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm10Regs.DBRED.bit.DBRED = EPWM_DB;
EPwm10Regs.DBFED.bit.DBFED = EPWM_DB;

EPwm11Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
EPwm11Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm11Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down
EPwm11Regs.TBCTL.bit.PHSEN = TB_ENABLE;    // Enable phase loading
EPwm11Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm11Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm11Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	// Enable sync
EPwm11Regs.TBPRD = EPWM_TIMER_TBPRD;       // Set timer period
EPwm11Regs.TBPHS.bit.TBPHS = EPWM_TIMER_TBPRD/2;        // Phase is 270

EPwm11Regs.AQCTLA.bit.CAU = AQ_SET;      	// Set PWM8A on Zero
EPwm11Regs.AQCTLA.bit.CAD = AQ_CLEAR;    	// Clear PWM8A on event A, up count

EPwm11Regs.AQCTLB.bit.CBU = AQ_SET;     // Set PWM8B on Zero
EPwm11Regs.AQCTLB.bit.CBD = AQ_CLEAR;    	// Clear PWM8B on event B, up count

EPwm11Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Period event
EPwm11Regs.ETSEL.bit.INTEN = 1;                // Enable INT
EPwm11Regs.ETPS.bit.INTPRD = ET_1ST;      // Generate INT on First event

EPwm11Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm11Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm11Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm11Regs.DBRED.bit.DBRED = EPWM_DB;
EPwm11Regs.DBFED.bit.DBFED = EPWM_DB;

  • 0
    TI__Mastermind 23600 points

    Hello,

    As seen in the TRM diagram, EPWM10 and EPWM11 are in a different part of the sync scheme as EPWM7/8/9. However, EPWM10 can use the EPWM7 sync-out signal as its sync in source, and through EPWM10, EPWM11 can also be synced to EPWM7 sync-out signal. On EPWM10/11, can confirm you:

    • Have phase shift enabled on both EPWMs (PHSEN register field)
    • Have EPWM10 SYNCIN be sourced from EPWM7 SYNCOUT (SYNCSELECT register)
    • Have EPWM10 SYNCOUT be sourced from its SYNCIN (SYNCOSELECT register field)

    Please double check these register values during run time after initialization. 

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Intellectual 320 points

    Hi Allison,

    My question is whether it is necessary to set up ePWM7 (even though I am not using it) to sync ePWM10 to ePWM8. I cannot use ePWM for my project. But I have tried it, and it did not work either.  Also, I have checked register values in debug mode, and they seems to be in order. Did you mean the SYNCSELECT register of SYNC_SOC_REGS Registers? Is it necessary to set that up since one of the sync source for ePWM10 is ePWM7 syncout? 

    I am getting the required phase shift when I used software sync on all the ePWM modules sequentially. Is it a viable method? Will it create any problems in the future?

    Regards,

    Murali

  • 0 in reply to Murali Manohar
    TI__Mastermind 23600 points

    Hello Murali, 

    Murali Manohar said:
    Did you mean the SYNCSELECT register of SYNC_SOC_REGS Registers?

    SYNCSELECT[EPWM10SYNCIN] is what I was referring to. Do you have this selected as well?

    Murali Manohar said:
    I cannot use ePWM for my project.

    Can you clarify this above statement please?

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Intellectual 320 points

    Hi Allison,

    Allison Nguyen said:
    Murali Manohar said:
    I cannot use ePWM for my project.

    Can you clarify this above statement please?

    I meant ePWM7. Sorry for the typo.

    Selecting SYNCSELECT[EPWM10SYNCIN] solves the issue only of I am configuring ePWM7. But the pins for ePWM7 are configured as CAN B in my design. Is there any other way to sync ePWM8 and ePWM10?

  • 0 in reply to Murali Manohar
    TI__Mastermind 23600 points

    Hi Murali,

    The only connection between the EPWM sync group that has EPWM8 and the group that has EPWMs 9/10/11 would be the external sync sources or EPWM7. If you cannot use EPWM7, you could try to route EPWM7 syncout through the EXTSYNCOUT XBAR GPIO to be used as an external sync in source for EPWM10/11. Is this something that would work for your application?

    Best Regards,

    Allison