TMS320F28379D: ADC register value is not appropriate

Hey Eunjin,

To figure this issue out, I’ll need the full code. Are you applying a DC voltage to the ADC pin for testing and verification? How did you set up your SoC for the ADC in the main control?

I recommend using the SysConfig tool to automatically generate the graphical initialization you need. You can then just copy it into your code later.

Best,

Masoud.

void setupADC(void)
{

//single ended

   AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
   AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

    EALLOW;
//ADCA


    AdcaRegs.ADCCTL2.bit.PRESCALE = 1;


    AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; //EOC --> 인터럽트 신호 발생

    AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; //ADC모듈 활성화

//ADCB
    AdcbRegs.ADCCTL2.bit.PRESCALE = 1;

    AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1; //EOC --> 인터럽트 신호 발생

    AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1; //ADC모듈 활성화

    EDIS;

    DELAY_US(1000);
}

void setupADCSOC(void)
{

    EALLOW;
//ADCA

   AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0;     // SOC0(=ADCA0)
   AdcaRegs.ADCSOC0CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0


   AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;     // SOC1(=ADCA1)
   AdcaRegs.ADCSOC1CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0
//
   AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2;     // SOC2(=ADCA2)
   AdcaRegs.ADCSOC2CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0

   AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;     // SOC3(=ADCA3)
   AdcaRegs.ADCSOC3CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0


   AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4;     // SOC4(=ADCA4)
   AdcaRegs.ADCSOC4CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0


   AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5;     // SOC5(=ADCA5)
   AdcaRegs.ADCSOC5CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcaRegs.ADCSOC5CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0

   AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 5; // End of SOC5 will set INT1 flag
   AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag
   AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared

   //ADCB

   AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0;  // SOC0(=ADCB0)
   AdcbRegs.ADCSOC0CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0

   AdcbRegs.ADCSOC1CTL.bit.CHSEL = 1;     //  SOC1(=ADCB1)
   AdcbRegs.ADCSOC1CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0

   AdcbRegs.ADCSOC2CTL.bit.CHSEL = 2;     //  SOC2(=ADCB2)
   AdcbRegs.ADCSOC2CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0

   AdcbRegs.ADCSOC3CTL.bit.CHSEL = 3;     //  SOC3(=ADCB3)
   AdcbRegs.ADCSOC3CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcbRegs.ADCSOC3CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0

   AdcbRegs.ADCSOC4CTL.bit.CHSEL = 4;     //  SOC4(=ADCB4)
   AdcbRegs.ADCSOC4CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcbRegs.ADCSOC4CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0

   AdcbRegs.ADCSOC5CTL.bit.CHSEL = 5;     //  SOC5(=ADCB5)
   AdcbRegs.ADCSOC5CTL.bit.ACQPS = 9;     // Sample window is 10 SYSCLK cycles
   AdcbRegs.ADCSOC5CTL.bit.TRIGSEL = 1;   // Trigger on CPUTIMER0

   //AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // End of SOC5 will set INT1 flag
  // AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag
   //AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared


   EDIS;
}

When observing the ADC values while operating the converter, the readings fluctuate as shown in the image above.