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Original question:

TMS320F28P650DH: Porting PTO on F28P65

TMS320F28P650SH: DAC deviation interference

Hui Cao22
Expert 1230 points
Part Number: TMS320F28P650SH


Tool/software:

The design of this DAC will have a deviation interference and interference time. For example, when the setting value is less than 1000LSB during the test, there will be a deviation of about 100LSB, and the deviation value is not necessarily. How do you assess this amount of interference and eliminate it.

  • 0
    TI__Expert 7100 points

    Hi Hui,

    Thanks for your patience.

    The DACH/L of each CMPSS module share some internal components, leading to a dependency between them. When the DAC value of one comparator (e.g., DACH) is updated-whether by software writing or by ramp generator- the output of the other DAC (e.g., DACL) can experience a temporary disturbance. This is  a characteristic of the shared architecture.

    To minimize or work around the CMPSS DAC output disturbance:

    1) Space out trip points: ensure the comparator inputs are at least 100LSBs apart from the DAC threshold when not actively tripping.

    2) Synchronize update: if you are using ISR to update DAC value, align it with PWM and use shadow register to load value cleanly, minimizing mid-cycle disturbances.

    3) Digital Filter:  Enable CMPSS digital filter to qualify the comparator outputs over multiple samples. This can mask transient disturbances shorter than the filter window (e.g., 200ns at 200MHz=40 cycles, so set SAMPWIN>40)