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Original question:

TMS320F2800137: Serial port burning

TMS320F2800137: EPWM wave generation proble

yong luo
Prodigy 230 points

Part Number: TMS320F2800137

Tool/software:

Hello expert!
S5 and S7 in the above figure are a set of ePWM (A and B), while S6 and S6 are a set of ePWM (A and B). When the sine value is positive, S5 and S7 complement each other at high frequencies, while S6 and S8 are at high levels with negative sine values. S6 and S8 complement each other at high frequencies, and S5 and S7 are at high levels. The sine cycle is 20ms.

I use the following configuration ePWM method:

SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
//5
EPWM_setActionQualifierAction(HB_PWM_1_2_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(HB_PWM_1_2_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
//7
EPWM_setActionQualifierAction(HB_PWM_1_2_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(HB_PWM_1_2_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setDeadBandDelayPolarity(HB_PWM_1_2_PWM_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
//6
EPWM_setActionQualifierAction(HB_PWM_3_4_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(HB_PWM_3_4_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
//8
EPWM_setActionQualifierAction(HB_PWM_3_4_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(HB_PWM_3_4_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

EPWM_setDeadBandDelayPolarity(HB_PWM_3_4_PWM_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_HIGH);

SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

But I am concerned that frequent disabling and enabling of PWM clocks may affect the system's waveform. Is this usage reasonable? Is there a simpler and more effective way to implement ePWMA and switch between high-frequency complementary waves and high levels?

best regard!

yours

thanks

  • 0
    TI__Expert 5310 points

    Yong Luo,

    During initial setup, its okay to disable clock, do the configuration and then enable clock. But during run time if you need to change configuration and if you disable clock, it will not be acceptable to topology because ePWM output behavior will become unpredictable during this transition. If its acceptable to the topology, you can trip all the ePWMs then change configuration and the clear that trip. During trip time which is generally one ePWM cycle, current in inductor will flow through body diode of the FETs.

    Regards,

    Sumit