Other Parts Discussed in Thread: C2000WARE, SYSCONFIG
Tool/software:
Hello TI Experts,
I hope you are all doing well,
I wanted to know if you have a proper guide for understanding linker command script especially while porting CPU Code to CLA for motor control applications. If you have any documentation regarding linker command scripts for CLA memory allocation it would be of immense help. I am facing an issue where my ported code works for 3 times and simply stops executing . I was wondering if its because the memory allocation is not enough. Any other insights into this would be helpful as well . I will attack my linker command script for reference. Thank you in advance.
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C
MEMORY
{
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
RAMM01 : origin = 0x0001B1, length = 0x000648
/* RAMM0 : origin = 0x0001B1, length = 0x00024F */
/* RAMM1 : origin = 0x000400, length = 0x0003F8 */ /* on-chip RAM block M1 */
/* RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 */ /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD0 : origin = 0x00C000, length = 0x002000
RAMD1 : origin = 0x00E000, length = 0x002000
RAMD2 : origin = 0x01A000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection
RAMD3 : origin = 0x01C000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection
RAMD4 : origin = 0x01E000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection
RAMD5 : origin = 0x020000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection
RAMLS01 : origin = 0x008000, length = 0x001000
/* RAMLS0 : origin = 0x008000, length = 0x000800 */
/* RAMLS1 : origin = 0x008800, length = 0x000800 */
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000
//RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
//RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory
RAMGS0 : origin = 0x010000, length = 0x002000
RAMGS1 : origin = 0x012000, length = 0x002000
RAMGS2 : origin = 0x014000, length = 0x002000
RAMGS3 : origin = 0x016000, length = 0x002000
RAMGS4 : origin = 0x018000, length = 0x002000
/* Flash Banks (128 sectors each) */
FLASH_BANK0 : origin = 0x080002, length = 0x1FFFE // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK1 : origin = 0x0A0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK3 : origin = 0x0E0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK4 : origin = 0x100000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
CLATOCPURAM : origin = 0x001480, length = 0x000080
CPUTOCLARAM : origin = 0x001500, length = 0x000080
CLATODMARAM : origin = 0x001680, length = 0x000080
DMATOCLARAM : origin = 0x001700, length = 0x000080
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
FPU32_FAST_TABLES : origin=0x3F667A, length = 0x081A
FPU64_FAST_TABLES : origin=0x3F6E94, length = 0x0D30
}
SECTIONS
{
codestart : > BEGIN, ALIGN(8)
.text : > FLASH_BANK0, ALIGN(8)
.cinit : > FLASH_BANK0, ALIGN(8)
.switch : > FLASH_BANK0, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM01
#if defined(__TI_EABI__)
.init_array : > FLASH_BANK0, ALIGN(8)
.bss : > RAMLS01
.bss:output : > RAMLS01
.bss:cio : > RAMLS01
.data : > RAMLS01
.sysmem : > RAMLS01
/* Initalized sections go in Flash */
.const : > FLASH_BANK0, ALIGN(8)
.binit : > FLASH_BANK0,
ALIGN(8)
#else
.pinit : > FLASH_BANK0, ALIGN(8)
.ebss : > RAMLS01
.esysmem : > RAMLS01
.cio : > RAMLS01
/* Initalized sections go in Flash */
.econst : > FLASH_BANK0, ALIGN(8)
#endif
ramgs0 : > RAMGS3, type=NOINIT
ramgs1 : > RAMGS3, type=NOINIT
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
/* CLA specific sections */
#if defined(__TI_EABI__)
Cla1Prog : LOAD = FLASH_BANK0,
RUN = RAMLS4,
LOAD_START(Cla1funcsLoadStart),
LOAD_END(Cla1funcsLoadEnd),
RUN_START(Cla1funcsRunStart),
LOAD_SIZE(Cla1funcsLoadSize),
ALIGN(8)
#else
Cla1Prog : LOAD = FLASH_BANK0,
RUN = RAMLS4,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0, ALIGN(8)
#endif
ClaData : > RAMLS5
Cla1ToCpuMsgRAM : > CLATOCPURAM, type=NOINIT
CpuToCla1MsgRAM : > CPUTOCLARAM, type=NOINIT
/* SFRA specific sections */
SFRA_F32_Data : > RAMGS3, ALIGN = 64
sfra_data : > RAMGS3
#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
//CLAscratch :
// { *.obj(CLAscratch)
// . += CLA_SCRATCHPAD_SIZE;
// *.obj(CLAscratch_end) } > RAMLS6
.scratchpad : > RAMLS6
.bss_cla : > RAMLS6
#if defined(__TI_EABI__)
.const_cla : LOAD = FLASH_BANK0,
RUN = RAMLS4,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
ALIGN(8)
#else
.const_cla : LOAD = FLASH_BANK0,
RUN = RAMLS4,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
ALIGN(8)
#endif
#endif //CLA_C
#if defined(__TI_EABI__)
GROUP
{
.TI.ramfunc {
}
ramfuncs
} LOAD = FLASH_BANK0,
RUN = RAMGS0 | RAMGS1 | RAMGS2,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
#else
.TI.ramfunc : {
} LOAD = FLASH_BANK0,
RUN = RAMGS0 | RAMGS1 | RAMGS2,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
/* Allocate FPU math areas: */
FPUmathTables : > FPU32_FAST_TABLES, TYPE = NOLOAD
CLA1mathTables { *(CLA1mathTables) } LOAD >> FLASH_BANK3 | FLASH_BANK4,
RUN >> RAMLS2 | RAMLS3,
TABLE(BINIT),
ALIGN(8)
}
Best Regards
Ashwin Bhaskar A
