Other Parts Discussed in Thread: C2000WARE
Tool/software:
Dear Experts,
I am working on a rectifier project and the program successfully boots from the FLASH without API. Now I would like to copy a section of the code(ADC ISR) in the RAM for better speed. I tried to understand the C2000ware example code and API document, Page 10 of F28379D API, followed the example code and modified my code. The CCS compiler doesnt flags and errors, however, the code would not run. It breaks at InitFlash() prompting "Break at address "0x3fe468" with no debug information available, or outside of program code"
#include "F28x_Project.h"
#include <math.h>
#include <stdio.h>
#include <pi.h>
#include <F021_F2837xD_C28x.h>
#define CPUCLK_FREQUENCY 200
#define WORDS_IN_FLASH_BUFFER 0xFF
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#define ramFuncSection ".TI.ramfunc"
#else
#define ramFuncSection "ramfuncs"
#endif
#endif
extern void InitSysCtrl(void);
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern void InitFlash(void);
extern void SeizeFlashPump(void);
#define TWO_PI 6.283185307179586476925286766559
interrupt void TimerOvf(void);
interrupt void ADCs_EOC(void);
void Initialize_GPIO(void);
void Custom_Init(void);
void timer0_init(void);
void PWM1_Init(void);
void Init_ADCs(void);
void X_bar(void);
int buff[100],buff2[100],buff3[100],i,b,c,d=0;
float pi,V_alpha,V_beta,Vd,Vq,R,Y,B,temp,temp2,theta,a;
void main(void)
{
InitSysCtrl();
Custom_Init();
PWM1_Init();
Init_ADCs();
DINT;
Initialize_GPIO();
InitPieCtrl();
InitFlash();
// SeizeFlashPump();
IER = 0x0000;
IFR = 0x0000;
InitPieCtrl();
InitPieVectTable();
EALLOW;
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; //ADC-A1
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieVectTable.TIMER0_INT = &TimerOvf;
PieVectTable.ADCA1_INT = &ADCs_EOC;
PieCtrlRegs.PIECTRL.bit.ENPIE= 1;
EDIS;
IER |= 3;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
timer0_init();
CpuTimer0Regs.TCR.bit.TSS=0;
while(1)
{
}
}
void Initialize_GPIO(void)
{
EALLOW;
//GPIO 18 - Xbar input
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0;
// GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0;
// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1;
// GpioCtrlRegs.GPADIR.bit.GPIO18 = 0;
// GpioCtrlRegs.GPACSEL3.bit.GPIO18 = 0;
// GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;
InputXbarRegs.INPUT5SELECT = 18;
// LED out
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO31 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO73= 1;
//PWMs
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; //ePWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; //ePWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; //ePWM3A
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; //ePWM4A
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; //ePWM5A
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; //ePWM6A
EDIS;
}
void Custom_Init(void)
{
EALLOW;
ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL=1;
ClkCfgRegs.AUXPLLMULT.bit.IMULT=20;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0;
ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; ///source initsysctrl
CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM5 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM6 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM7 = 1;
CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
DevCfgRegs.CPUSEL0.bit.EPWM1 = 0;
EDIS;
}
void timer0_init(void)
{
EALLOW;
CpuTimer0Regs.PRD.bit.MSW = 0x0004;
CpuTimer0Regs.PRD.bit.LSW = 0x0080;
CpuTimer0Regs.TPR.bit.TDDR = 0x0013;
CpuTimer0Regs.TCR.bit.TIE= 1;
CpuTimer0Regs.TCR.bit.TSS=1;
CpuTimer0Regs.TCR.bit.FREE=0;
CpuTimer0Regs.TCR.bit.TRB=0;
EDIS;
}
void TimerOvf(void)
{
b= b+1;
if(b>3)
{
EPwm1Regs.TBSTS.bit.SYNCI=1;
b=1;
}
if(EPwm1Regs.TBSTS.bit.SYNCI==1)
{
GpioDataRegs.GPBSET.bit.GPIO34=1;
GpioDataRegs.GPASET.bit.GPIO31=1;
}
CpuTimer0Regs.TCR.bit.TIF = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
#pragma CODE_SECTION(ADCs_EOC, ramFuncSection);
void ADCs_EOC(void)
{
Vd=100;
Vq=0;
c =c +1;
if(c>3)
{
c=0;
}
a = AdcaResultRegs.ADCRESULT0; //Va
temp = (a*62500)/4095;
R = 1000-a;
pi = PI(R);
EPwm1Regs.CMPA.bit.CMPA = temp;
EPwm1Regs.CMPB.bit.CMPB = temp + 9000;
EPwm2Regs.CMPA.bit.CMPA = temp;
EPwm2Regs.CMPB.bit.CMPB = temp + 9000;
EPwm3Regs.CMPA.bit.CMPA = temp;
EPwm3Regs.CMPB.bit.CMPB = temp + 9000;
EPwm4Regs.CMPA.bit.CMPA = temp;
EPwm4Regs.CMPB.bit.CMPB = temp + 9000;
EPwm5Regs.CMPA.bit.CMPA = temp;
EPwm5Regs.CMPB.bit.CMPB = temp + 9000;
EPwm6Regs.CMPA.bit.CMPA = temp;
EPwm6Regs.CMPB.bit.CMPB = temp + 9000;
//sine generation
if(i>100)
{
i=0;
}
theta = TWO_PI*i/100;
R = 100*sin(theta);
V_alpha = Vd*cos(theta) - Vq*sin(theta);
V_beta = Vd*sin(theta) + Vq*cos(theta);
R = V_alpha;
Y = -(0.5*V_alpha)+(0.866025*V_beta);
B = -(0.5*V_alpha)-(0.866025*V_beta);
buff[i] = R;
buff2[i]= Y;
buff3[i]= B;
i= i+1;
EPwm7Regs.ETCLR.bit.SOCA = 1;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
void PWM1_Init(void)
{
EALLOW;
//R Phase
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm1Regs.TBPRD = 62500; // Set timer period
EPwm1Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 2; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = 4;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 0;
// Setup shadow register load on ZERO
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;
// Set Compare values
// Set compare A value
// Set actions
EPwm1Regs.AQCTLA.all = 0;
EPwm1Regs.AQCTLA.bit.CAU = 2; // Set PWM1A on TBCTR = CMPA
EPwm1Regs.AQCTLA.bit.CBU = 1; // Clear PWM1A on TBCTR = CMPB= CMPA + 100
//Y0 phase
EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm2Regs.TBPRD = 62500; // Set timer period
EPwm2Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm2Regs.TBPHS.bit.TBPHS = 10417; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 2; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = 4;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;
// Setup shadow register load on ZERO
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;
// Set Compare values+
// Set compare A value
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = 2; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CBU = 1; // Clear PWM1A on event A, up count
//B Phase
EPwm3Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm3Regs.TBPRD = 62500; // Set timer period
EPwm3Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm3Regs.TBPHS.bit.TBPHS = 20833; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 2; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = 4;
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;
// Setup shadow register load on ZERO
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;
// Set Compare values+
// Set compare A value
// Set actions
EPwm3Regs.AQCTLA.bit.CAU = 2; // Set PWM1A on Zero
EPwm3Regs.AQCTLA.bit.CBU = 1; // Clear PWM1A on event A, up count
//R0 phase
EPwm4Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm4Regs.TBPRD = 62500; // Set timer period
EPwm4Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm4Regs.TBPHS.bit.TBPHS = 31250; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 2; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = 4;
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0;
// Setup shadow register load on ZERO
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm4Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm4Regs.CMPCTL.bit.LOADBMODE = 0;
// Set Compare values+
// Set compare A value
// Set actions
EPwm4Regs.AQCTLA.bit.CAU = 2; // Set PWM1A on Zero
EPwm4Regs.AQCTLA.bit.CBU = 1; // Clear PWM1A on event A, up count
//Y phase
EPwm5Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm5Regs.TBPRD = 62500; // Set timer period
EPwm5Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm5Regs.TBPHS.bit.TBPHS = 36458; // Phase is 0
EPwm5Regs.TBCTR = 0x0000; // Clear counter
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 2; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = 4;
EPwm5Regs.TBCTL.bit.SYNCOSEL = 0;
// Setup shadow register load on ZERO
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADBMODE = 0;
// Set Compare values+
// Set compare A value
// Set actions
EPwm5Regs.AQCTLA.bit.CAU = 2; // Set PWM1A on Zero
EPwm5Regs.AQCTLA.bit.CBU = 1; // Clear PWM1A on event A, up count
//B0 Phase
EPwm6Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm6Regs.TBPRD = 62500; // Set timer period
EPwm6Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm6Regs.TBPHS.bit.TBPHS = 52083; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 2; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = 4;
EPwm6Regs.TBCTL.bit.SYNCOSEL = 0;
// Setup shadow register load on ZERO
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm6Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm6Regs.CMPCTL.bit.LOADBMODE = 0;
// Set Compare values+
// Set compare A value
// Set actions
EPwm6Regs.AQCTLA.bit.CAU = 2; // Set PWM1A on Zero
EPwm6Regs.AQCTLA.bit.CBU = 1; // Clear PWM1A on event A, up count
//ADC trigger
EPwm7Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm7Regs.TBPRD = 10000; // Set timer period
EPwm7Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm7Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm7Regs.TBCTR = 0x0000; // Clear counter
EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm7Regs.TBCTL.bit.CLKDIV = 0;
EPwm7Regs.TBCTL.bit.SYNCOSEL = 0;
// Setup shadow register load on ZERO
EPwm7Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm7Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm7Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm7Regs.CMPCTL.bit.LOADBMODE = 0;
//SOCA to ADC
EPwm7Regs.ETSEL.bit.SOCAEN=1;
EPwm7Regs.ETSEL.bit.SOCASEL=1;
EPwm7Regs.ETPS.bit.SOCAPRD = 1;
EPwm7Regs.ETCLR.bit.SOCA = 1;
EDIS;
}
void Init_ADCs(void)
{
EALLOW;
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
// DELAY_US(1);
AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
AdccRegs.ADCCTL2.bit.PRESCALE = 6;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; //SOC1 will convert pin A1
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2; //SOC2 will convert pin A2
AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3; //SOC3 will convert pin A3
AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4; //SOC4 will convert pin A4
AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5; //SOC5 will convert pin A5
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert pin B2
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3; //SOC1 will convert pin B3
AdcbRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC2 will convert pin B4
AdcbRegs.ADCSOC3CTL.bit.CHSEL = 5; //SOC3 will convert pin B5
AdccRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert pin C2
AdccRegs.ADCSOC1CTL.bit.CHSEL = 3; //SOC1 will convert pin C3
AdccRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC2 will convert pin C4
AdccRegs.ADCSOC3CTL.bit.CHSEL = 5; //SOC3 will convert pin C5
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC4CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC5CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1;
AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 11;
AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 17;
AdcbRegs.ADCBURSTCTL.bit.BURSTEN = 1;
AdcbRegs.ADCBURSTCTL.bit.BURSTSIZE = 11;
AdcbRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 17;
AdccRegs.ADCBURSTCTL.bit.BURSTEN = 1;
AdccRegs.ADCBURSTCTL.bit.BURSTSIZE = 11;
AdccRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 17;
//interrupt
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0;
EDIS;
}
Regards,
Rajesh.
