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TMS320F28P650DK: Do CPU2 & CLA self test at the same test

Leo Wu
Intellectual 1540 points

Part Number: TMS320F28P650DK

Tool/software:

Hi experts,

In the F28P65x_CLA_STL_API_User's_Guide.pdf 

In the F28P65x_C28x_STL_API_User's_Guide.pdf

Both of CPU2 and CLA test need to use 0x8000. How to do the CPU2 & CLA test at the same time?

Thanks,

Leo

  • 0
    TI__Guru 54365 points

    Hi Leo,

    Each CPU subsystem has its own LS0RAM, so it shouldn't be a problem. The CLA_STL only needs to run in the CPU1 subsystem and the C28x_STL only needs to run in the CPU2 subsystem.

    Whitney

  • 0 in reply to Whitney Dewey
    TI__Intellectual 1285 points

    Hi Whitney,

    Thanks. Customer found the content of the reply is inconsistent with the content in the manual and the results of our tests. These are as follows:

    1. Contents of the manual:

      (1). According to the P65 data manual description, CPU1 has RAMLS0, while CPU2 does not have RAMLS0, on CPU2 RAMLS0-RAMLS4 unified RAMD2. Refer to the following figure, TMS320F28P65x Real-Time Microcontrollers Manual:

      (2). RAMLSD2 mentioned above is shared between CPU1 and CPU2, i.e. only one CPU is available for the same address.

    2.Our test results:

      (1). Only CLA uses LS0 8000 address self-test OK;

      (2). Only CPU2 self test with 8000 address of D2 OK;

      (3). CLA and CPU2 use 8000 address, NG;

    To sum up: CLA and CPU2 cannot be self-tested at the same time because of a vector address conflict. Please help with confirmation.

     

  • 0 in reply to Moon Wang
    TI__Guru 54365 points

    Sorry, for the confusion--I forgot it was D2 on CPU2. I still think it's fine to use them at the same time though. My understanding is that they're not unified, but rather LS0 and D2 are different memories. Notice that when CPU1 owns D2, it's mapped to a totally different address (0x1A000).

    Whitney