Dear Experts,
I am trying to trigger the CLA using ADCAINT1 and it would not get triggered! I even force the trigger using Cla1Regs.MIFRC.bit.INT1 = 1, but still it would not.
Please let know where I have gone wrong. Here is the Project and the code for your reference.
#include "F28x_Project.h"
#include <math.h>
#include <stdio.h>
#include "Solar_CLA.h"
#include "CLA_Shared.h"
extern void InitSysCtrl(void);
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern interrupt void Cla1Task1();
#define TWO_PI 6.283185307179586476925286766559
interrupt void ADCs_EOC(void);
interrupt void cla_isr(void);
void Initialize_GPIO(void);
void Custom_Init(void);
void PWM1_Init(void);
void Init_ADCs(void);
void X_bar(void);
void InitCla(void);
int buff[100],buff2[100],buff3[100],i,b,c,d,cla=0;
float pi,V_alpha,V_beta,Vd,Vq,R,Y,B,temp,temp2,theta,a=0;
void main(void)
{
InitSysCtrl();
Custom_Init();
PWM1_Init();
Init_ADCs();
DINT;
Initialize_GPIO();
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieCtrl();
InitPieVectTable();
InitCla();
EALLOW;
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; //ADC-A1
PieCtrlRegs.PIEIER11.bit.INTx1 = 1; //cla-isr
PieVectTable.ADCA1_INT = &ADCs_EOC;
PieVectTable.CLA1_1_INT = &cla_isr;
PieCtrlRegs.PIECTRL.bit.ENPIE= 1;
EDIS;
IER |= 1025;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
while(1)
{
}
}
void Initialize_GPIO(void)
{
EALLOW;
//GPIO 18 - Xbar input
/* GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0;
// GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0;
// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1;
// GpioCtrlRegs.GPADIR.bit.GPIO18 = 0;
// GpioCtrlRegs.GPACSEL3.bit.GPIO18 = 0;
// GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;
InputXbarRegs.INPUT5SELECT = 18;
*/
// LED out
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO31 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO73= 1;
//PWMs
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; //ePWM1A
EDIS;
}
void Custom_Init(void)
{
EALLOW;
ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL=1;
ClkCfgRegs.AUXPLLMULT.bit.IMULT=20;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0;
ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; ///source initsysctrl
CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM5 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM6 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM7 = 1;
CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
DevCfgRegs.CPUSEL0.bit.EPWM1 = 0;
EDIS;
}
void ADCs_EOC(void)
{
EALLOW;
Cla1Regs.MIFRC.bit.INT1 = 1;
EDIS;
Vd=100;
Vq=0;
a = AdcaResultRegs.ADCRESULT0; //Va
temp = (a*62500)/4095;
EPwm1Regs.CMPA.bit.CMPA = temp;
EPwm1Regs.CMPB.bit.CMPB = temp + 9000;
if(i>100)
{
i=0;
}
theta = TWO_PI*i/100;
V_alpha = Vd*cos(theta) - Vq*sin(theta);
V_beta = Vd*sin(theta) + Vq*cos(theta);
R = V_alpha;
Y = (0.866025*V_beta)-(0.5*V_alpha);
B = -(0.5*V_alpha)-(0.866025*V_beta);
buff2[i] = R;
buff[i]= Y;
buff3[i]= B;
i= i+1;
EPwm1Regs.ETCLR.bit.SOCA = 1;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
void cla_isr(void)
{
cla=cla+1;
if(cla>10)
{
cla = 0;
}
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
Cla1Regs.MCTL.bit.IACKE = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
}
void PWM1_Init(void)
{
EALLOW;
//R Phase
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm1Regs.TBPRD = 62500; // Set timer period
EPwm1Regs.TBCTL.bit.PHSEN = 0; // 1 for external SYNC
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 2; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = 4;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;
// Setup shadow register load on ZERO
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;
// Set Compare values
// Set compare A value
// Set actions
EPwm1Regs.AQCTLA.all = 0;
EPwm1Regs.AQCTLA.bit.CAU = 2; // Set PWM1A on TBCTR = CMPA
EPwm1Regs.AQCTLA.bit.CBU = 1; // Clear PWM1A on TBCTR = CMPB= CMPA + 100
//SOCA to ADC
EPwm1Regs.ETSEL.bit.SOCAEN=1;
EPwm1Regs.ETSEL.bit.SOCASEL=1;
EPwm1Regs.ETPS.bit.SOCAPRD = 1;
EPwm1Regs.ETCLR.bit.SOCA = 1;
EDIS;
}
void InitCla(void)
{
EALLOW;
DevCfgRegs.DC1.bit.CPU1_CLA1 = 1;
Cla1Regs.MCTL.bit.HARDRESET = 1;
Cla1Regs.MCTL.bit.SOFTRESET = 1;
Cla1Regs.MCTL.bit.IACKE = 1;
Cla1Regs.MIER.bit.INT1 = 1; //enable Task1
Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1); //vector address
Cla1Regs.MICLROVF.bit.INT1 = 1;
MemCfgRegs.LSxMSEL.all = 0;
MemCfgRegs.LSxCLAPGM.all=0;
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1; //LS0 for CLA 8000 to 87FF (2K words) more than enough I guess for now
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 1; //LS0 for program memory
MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1; //LS1 for CLA 8800 to 8FFF (2K words)
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0; //LS1 for Data memory
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1 = 1; //ADCAINT1
EDIS;
}
void Init_ADCs(void)
{
EALLOW;
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
// DELAY_US(1);
AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
AdccRegs.ADCCTL2.bit.PRESCALE = 6;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; //SOC1 will convert pin A1
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2; //SOC2 will convert pin A2
AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3; //SOC3 will convert pin A3
AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4; //SOC4 will convert pin A4
AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5; //SOC5 will convert pin A5
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC4CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC5CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1;
AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 11;
AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 5;
//interrupt
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 05;
EDIS;
}
Regards,
Rajesh.
