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TMS320F28P650DH: SPI-INT

nie chunying
Intellectual 350 points
Part Number: TMS320F28P650DH


Tool/software:

Hello expert, I want to use DSP(slave machine)SPI and PC host computer (host) to transmit data to each other, SPI receives variable length data, and sends variable length data. My purpose is to reduce the CPU burden,

1.if the DMA send interrupt to send indefinite length data, SPI no FIFO transmission complete interrupt (INT_FLAG) to receive indefinite length data (more than 16 16-bit data); Can I do this configuration?

2.Will it increase the CPU burden?

3.If the DSP receives 40 16bit data, then the DSP carries out three transmission completion interrupt (INT_FLAG), the first transmission completion interrupt receives 16 16bit data, the second transmission completion interrupt receives 16 16bit data, the third transmission completion interrupt receives 8 16bit data, I have to understand right

  • 0
    TI__Expert 3315 points

    Hi,

    1) Could you explain the desired configurations a bit more in detail? I'm not quite sure what you mean by indefinite length data.

    2) Yes, certainly. You will be freeing up the CPU from having to move data between SPI buffers and memory

    3) This method would require you to change the FIFO interrupt trigger level from 16 to 8 in between the 2nd and 3rd data transmissions, which may not always be possible. It might be easier to set the FIFO trigger level to 8, and receive 5 times instead (or some other such combination which doesn't require changing FIFO levels between pieces of a single group of data)

    Regards,

    Arnav

  • 0 in reply to Arnav Menon R
    Intellectual 350 points

    1）Indefinite length data means that the length of the sent data is uncertain and the length of the received data is uncertain

    2）My ultimate goal is to reduce the CPU burden, what scheduling method do you suggest I use easily