Tool/software:
Hi team,
I ask this question for my customer,
if cpu is executing ISR, and the time exceeds the interval between interruptions, so the next interrupt will generate when cpu in ISR, what will happen?
The overflow flag will be set, but it don't block further interrupts from propagating to the PIE module? Is overflow interrupts passed on to the PIE module?
For example, in t1, a interrupt is generating, CPU enter ISR; in t1+t0, the same interrupt generate, CPU still in ISR; in t1+t0+t2(t2<t0), CPU return from ISR; in t1+2t0, the same interrupt generate again.
Is CPU will enter to ISR in t1+t0+t2? Is CPU will enter to ISR in t1+2t0 if customer don't clear the overflow flag? Will there be unpredictable results?
BRs
Shuqing
