Tool/software:
Hi all,
The CAN receive is acknowledged by the microcontroller since the acknowledgement error is not shown in the canalyzer. But the interrupt for can receive is not occurring. INT9.9 is used. Standard ID filter is used to filter two message IDs. The message ID for filters is the same as that of the message transmitted by the canalyzer. What could be the issue?
The register values are shared below:
Core Registers Core Registers
IER 0x0301 Interrupt Enable Register [Core]
RTOSINT 0 Real-time operating system interrupt enable bit
DLOGINT 0 Data log interrupt enable bit
INT14 0
INT13 0
INT12 0
INT11 0
INT10 1
INT9 1
INT8 0
INT7 0
INT6 0
INT5 0
INT4 0
INT3 0
INT2 0
INT1 1
McanaRegs MCAN Registers
MCAN_CREL 0x32380608
MCAN_CCCR 0x00000100
MCAN_NBTP 0x0E030A07
MCAN_TSCC 0x00000000
MCAN_TSCV 0x00000000
MCAN_TOCC 0xFFFF0000
MCAN_TOCV 0x0000FFFF
MCAN_ECR 0x00100036
CEL 00010000 CAN Error Logging
RP 0 Receive Error Passive
REC 0000000 Receive Error Counter
TEC 00110110 Transmit Error Counter
MCAN_PSR 0x00002708
TDCV 0000000 Transmitter Delay Compensation Value
PXE 0 Protocol Exception Event
RFDF 1 Received a CAN FD Message
RBRS 0 BRS Flag of Last Received CAN FD Message
RESI 0 ESI Flag of Last Received CAN FD Message
DLEC 111 Data Phase Last Error Code
BO 0 Bus_Off Status
EW 0 Warning Status
EP 0 Error Passive
ACT 01 Node Activity
LEC 000 Last Error Code
MCAN_TDCR 0x00000000 MCAN Transmitter Delay Compensation Register [Memory Mapped]
MCAN_IR 0x09800A08 MCAN Interrupt Register [Memory Mapped]
MCAN_IE 0x3FFFFFFF MCAN Interrupt Enable [Memory Mapped]
ARAE 1 Access to Reserved Address Enable
PEDE 1 Protocol Error in Data Phase Enable
PEAE 1 Protocol Error in Arbitration Phase Enable
WDIE 1 Watchdog Interrupt Enable
BOE 1 Bus_Off Status Enable
EWE 1 Warning Status Enable
EPE 1 Error Passive Enable
ELOE 1 Error Logging Overflow Enable
BEUE 1 Bit Error Uncorrected Enable
BECE 1 Bit Error Corrected Enable
DRXE 1 Message Stored to Dedicated Rx Buffer Enable
TOOE 1 Timeout Occurred Enable
MRAFE 1 Message RAM Access Failure Enable
TSWE 1 Timestamp Wraparound Enable
TEFLE 1 Tx Event FIFO Element Lost Enable
TEFFE 1 Tx Event FIFO Full Enable
TEFWE 1 Tx Event FIFO Watermark Reached Enable
TEFNE 1 Tx Event FIFO New Entry Enable
TFEE 1 Tx FIFO Empty Enable
TCFE 1 Transmission Cancellation Finished Enable
TCE 1 Transmission Completed Enable
HPME 1 High Priority Message Enable
RF1LE 1 Rx FIFO 1 Message Lost Enable
RF1FE 1 Rx FIFO 1 Full Enable
RF1WE 1 Rx FIFO 1 Watermark Reached Enable
RF1NE 1 Rx FIFO 1 New Message Enable
RF0LE 1 Rx FIFO 0 Message Lost Enable
RF0FE 1 Rx FIFO 0 Full Enable
RF0WE 1 Rx FIFO 0 Watermark Reached Enable
RF0NE 1 Rx FIFO 0 New Message Enable
MCAN_ILS 0x00000000 MCAN Interrupt Line Select [Memory Mapped]
MCAN_ILE 0x00000001 MCAN Interrupt Line Enable [Memory Mapped]
EINT1 0 Enable Interrupt Line 1
EINT0 1 Enable Interrupt Line 0
MCAN_GFC 0x00000000 MCAN Global Filter Configuration [Memory Mapped]
MCAN_SIDFC 0x00020000 MCAN Standard ID Filter Configuration [Memory Mapped]
LSS 00000010 List Size Standard
FLSSA 00000000000000 Filter List Standard Start Address
MCAN_XIDFC 0x00000020 MCAN Extended ID Filter Configuration [Memory Mapped]
LSE 0000000 List Size Extended
FLESA 00000000001000 Filter List Extended Start Address
MCAN_XIDAM 0x1FFFFFFF MCAN Extended ID and Mask [Memory Mapped]
MCAN_HPMS 0x00000000 MCAN High Priority Message Status [Memory Mapped]
MCAN_NDAT1 0x00000000 MCAN New Data 1 [Memory Mapped]
MCAN_NDAT2 0x00000000 MCAN New Data 2 [Memory Mapped]
MCAN_RXF0C 0x00000000 MCAN Rx FIFO 0 Configuration [Memory Mapped]
MCAN_RXF0S 0x02000000 MCAN Rx FIFO 0 Status [Memory Mapped]
MCAN_RXF0A 0x00000000 MCAN Rx FIFO 0 Acknowledge [Memory Mapped]
MCAN_RXBC 0x00000020 MCAN Rx Buffer Configuration [Memory Mapped]
MCAN_RXF1C 0x00000000 MCAN Rx FIFO 1 Configuration [Memory Mapped]
MCAN_RXF1S 0x00000000 MCAN Rx FIFO 1 Status [Memory Mapped]
MCAN_RXF1A 0x00000000 MCAN Rx FIFO 1 Acknowledge [Memory Mapped]
MCAN_RXESC 0x00000700 MCAN Rx Buffer / FIFO Element Size Configuration [Memory Mapped]
MCAN_TXBC 0x05050170 MCAN Tx Buffer Configuration [Memory Mapped]
MCAN_TXFQS 0x00090905 MCAN Tx FIFO / Queue Status [Memory Mapped]
MCAN_TXESC 0x00000007 MCAN Tx Buffer Element Size Configuration [Memory Mapped]
MCAN_TXBRP 0x00000000 MCAN Tx Buffer Request Pending [Memory Mapped]
MCAN_TXBAR 0x00000000 MCAN Tx Buffer Add Request [Memory Mapped]
MCAN_TXBCR 0x00000000 MCAN Tx Buffer Cancellation Request [Memory Mapped]
MCAN_TXBTO 0x000003E0 MCAN Tx Buffer Transmission Occurred [Memory Mapped]
MCAN_TXBCF 0x00000000 MCAN Tx Buffer Cancellation Finished [Memory Mapped]
MCAN_TXBTIE 0x000003E0 MCAN Tx Buffer Transmission Interrupt Enable [Memory Mapped]
MCAN_TXBCIE 0x00000000 MCAN Tx Buffer Cancellation Finished Interrupt Enable [Memory Mapped]
MCAN_TXEFC 0x00050B60 MCAN Tx Event FIFO Configuration [Memory Mapped]
MCAN_TXEFS 0x00000000 MCAN Tx Event FIFO Status [Memory Mapped]
MCAN_TXEFA 0x00000000 MCAN Tx Event FIFO Acknowledge [Memory Mapped]
McanaErrorRegs MCAN ERROR Registers
MCANERR_REV 0x66A0EA00 MCAN Error Aggregator Revision Register [Memory Mapped]
MCANERR_VECTOR 0x00000000 MCAN ECC Vector Register [Memory Mapped]
MCANERR_STAT 0x00000002 MCAN Error Misc Status [Memory Mapped]
McanssaRegs MCANSS Registers
MCANSS_PID 0x68E05101 MCAN Subsystem Revision Register [Memory Mapped]
MCANSS_CTRL 0x00000008 MCAN Subsystem Control Register [Memory Mapped]
EXT_TS_CNTR_EN 0 External Timestamp Counter Enable
AUTOWAKEUP 0 Automatic Wakeup Enable
WAKEUPREQEN 0 Wakeup Request Enable
DBGSUSP_FREE 1 Debug Suspend Free
MCANSS_STAT 0x00000006 MCAN Subsystem Status Register [Memory Mapped]
ENABLE_FDOE 1 Flexible Datarate Operation Enable
MEM_INIT_DONE 1 Memory Initialization Done
RESET 0 Soft Reset Status
MCANSS_ICS 0x00000000
MCANSS_IRS 0x00000000
MCANSS_IECS 0x00000000
MCANSS_IE 0x00000000
MCANSS_IES 0x00000000
PieCtrlRegs PIE CTRL Registers
PIECTRL 0x0D43 ePIE Control Register [Memory Mapped]
PIEVECT 000011010100001 PIE Vector Address
ENPIE 1 PIE Enable
PIEACK 0x0000 Interrupt Acknowledge Register [Memory Mapped]
PIEIER1 0x0047 Interrupt Group 1 Enable Register [Memory Mapped]
INTx7 1 Enable for Interrupt 1.7
INTx3 1 Enable for Interrupt 1.3
INTx2 1 Enable for Interrupt 1.2
INTx1 1 Enable for Interrupt 1.1
PIEIFR1 0x0200 Interrupt Group 1 Flag Register [Memory Mapped]
INTx10 1 Flag for Interrupt 1.10
PIEIER9 0x0100 Interrupt Group 9 Enable Register [Memory Mapped]
INTx9 1 Enable for Interrupt 9.9
PIEIER10 0x0EEE Interrupt Group 10 Enable Register [Memory Mapped]
INTx12 1 Enable for Interrupt 10.12
INTx11 1 Enable for Interrupt 10.11
INTx10 1 Enable for Interrupt 10.10
INTx8 1 Enable for Interrupt 10.8
INTx7 1 Enable for Interrupt 10.7
INTx6 1 Enable for Interrupt 10.6
INTx4 1 Enable for Interrupt 10.4
INTx3 1 Enable for Interrupt 10.3
INTx2 1 Enable for Interrupt 10.2
