• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 82 subscribers
  • Views 197 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28P550SG: SCI communication parity check error

JIANJUN ZHANG
Prodigy 120 points
Part Number: TMS320F28P550SG


Tool/software:

HI TI experts,

        Two 28P55SG8 devices communicate via SCI. 

        FIFIO： Enable; Baud rate: 38400; Odd verification;
       Question:

       The data received in RXBUF is correct, but the parity bit frequently reports errors. Using the oscilloscope captures the TX and RX data, and is equipped with it. What may be the possible reasons for the errors?

       thanks！

  • 0
    Prodigy 120 points

    8-bit data received correctly, status register SCIRXST shows verification error，PE=1.

  • 0
    Prodigy 120 points

    Part Number: TMS320F28P550SG

    Tool/software:

    Hi TI experts,


             Two 28P55SG8 are used for SCI communication, and BUF data is read using a state query method. The SCI clock frequency is 150M/4=37.5M, the baud rate is 38400, the odd parity is enabled, and the FIFO function is enabled. One side reads the SCI receiving status register SCIRXST, and the SCI parity error flag is frequently set to 1. The FIFO status register SCIFFRX is read, and the receiving FIFO overflow bit RXFFOVF is frequently set to 1;
           In addition, reading the 8-bit data bits received by SCI is correct; Checked the SCI receiving and sending port configurations, and no issues were found.
    Question:

          What are the reasons for the above phenomenon? Or if the above problems can be solved through software configuration?

    thanks.

  • 0 in reply to JIANJUN ZHANG
    TI__Mastermind 21100 points

    Hi Jianjun,

    I apologize for the delay.

    For the receiving F28P55x device, are you using an interrupt-based approach or a polling approach? If the overflow bit is being set, the data in the RX FIFO isn't being read out fast enough.

    For the parity error you are seeing, can you verify that the SCI module on both devices is configured for odd parity? It is strange that the parity flag is being raised if all the received data is correct.

    Is the receiving project only doing the SCI operation you described? Or are there other peripherals being used / ISRs being called in the project as well?

    Best Regards,

    Delaney