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TMS320F28377D: I would like to know whether handling ADC calibration process on CPU2 is acceptable.

Sang-il Nam
Expert 2550 points
Part Number: TMS320F28377D


Tool/software:

Hi,

In the F2837x TRM, section 11.11 ADC Calibration, it is stated that CPU1 must apply trim data for the ADC and other analog circuits.

Does this mean that when operating the ADC or DAC from CPU2, CPU1 must initialize and calibrate the circuit before transferring ownership to CPU2 using the CPUSELx bits?

Looking at TI's F2837x multicore example (device_support/dual/adc_epwm), CPU1 transfers ownership of the ADC circuit to CPU2 by manipulating the CPUSELx bits. Then, in the CPU2-side code, the AdcSetMode() function is called, followed by ADC power-on (modifying the ADCPWDNZ bit).

Since the AdcSetMode() function appears to include code for applying calibration data, I would like to confirm whether handling this calibration process on CPU2 is acceptable.

Thanks and regards,
Sang-il

  • 0
    TI__Expert 4350 points

    Hello,

    It's not okay to handle calibration solely from CPU2. Only CPU1 is responsible for retrieving and applying the correct factory trim values, and it needs to complete the calibration before transferring ownership. In the example given, if "AdcSetMode()" is called from CPU2 before CPU1 has set the trim values, the calibration could use incorrect values, since CPU2 doesn't have access to those OTP locations. I believe the example mainly illustrates peripheral sharing rather than complete initialization, and I'll check with our expert to verify this.

    Best,
    Masoud

  • 0 in reply to Masoud Farhadi
    Expert 2550 points

    Hello,

    Thank you for your response.

    As far as I understand, that in order to meet the ADC specifications presented in the F2837xD's datasheet, the calibration routine included in the AdcSetMode() function must be executed in addition to the Device_cal() routine, which is processed during the chip's boot sequence.

    In other words, CPU1 should not simply transfer ownership of the ADC to CPU2. I think that CPU1 should apply the calibration data to the ADC module through the AdcSetMode() function, set the signal mode and resolution, and then transfer ownership to CPU2.

    Please share the results confirmed by the expert you mentioned above through this post.

    Thanks and regards,
    Sang-il

  • 0 in reply to Sang-il Nam
    TI__Expert 4350 points

    Sang-il,

    As we discussed before, the ADC calibration values should be called with CPU1. This can be tested by trying to use AdcSetMode() function with CPU2 which cannot write the call the right trim values in OTP address (0x0703AC). Also, ownership should be transferred to CPU2 to have the right conversion.

    Best Regards,

    Masoud

  • 0 in reply to Masoud Farhadi
    TI__Expert 4350 points

    I asked SDK team to fix this issue. I have one more suggestion here. You can copy the calibration values with CPU1 to the part of the memory which CPU 2 can read it. Then you should be able to calibrate it with both CPUs.

    Best Regards,

    Masoud

  • 0 in reply to Masoud Farhadi
    Expert 2550 points

    Dear Masoud Farhadi,

    Your proposed method is as follows:

    a) CPU1 reads the trim values in the OTP region of CPU1 and stores them in a shared memory area(ex. GSxRAM) accessible by CPU2.
    b) CPU2 reads the trim values from the shared memory and applies it to the ADC TRIM registers (ADCOFFTRIM, ADCINLTRIM1~6).

    Is the reason for your proposal that there could be potential issues if CPU1 applies the trim value to the ADC module and then hands over ownership to CPU2, which subsequently activates ADCCTL1[ADCPWDNZ] and operates the ADC module?

    To apply your proposed method to my firmware, I would not be able to use the AdcSetMode( ) function provided by TI. Instead, I would need to manually implement similar code to initialize the ADC. Since there is a risk of making mistakes in this process, I would prefer to use a TI-validated solution if possible.

    If there is any documentation or example code that provides a precise initialization procedure for CPU2 (Slave Core) to operate the ADC module within the electrical specifications outlined in the datasheet, I would appreciate receiving it.

    Thanks and regards,
    Sang-il