TMS320F28P559SJ-Q1: Edge detection of ePWM for CMPSS

Hello,

I will take a look and reply in a timely manner.

Thank you.

One more question please.

Q:Can ePWM modules sync itself?

This is EPWM8 settings.

In our intention, when DCA Event 1 occure, EPWM8 make Sync Out Pulse, and get it as Sync in Pulse Source, so EPWM8 is synced by itself (->Counter initialized).

Is it correct?

Hello Ryushi,

Firstly, to help me more understand, how do you generate your ePWM, how are you setting it and clearing it? What is your overall application here? Do you intend to generate CMPSS Ramp DAC on falling edges of A and B waveforms of same PWM and you are not able to achieve it?

Best regards,

Stevan D.

Hello Steven,

1.
This PWM is intended to control DCDC Converter.

2.
CMPSS or CMPx(as time limit) make PWMA low, and CMPSS or period(as time limit) make PWMA high.

So, Ramp of the CMPSS should be reset when PWMA changes = edges.

Best regards.

Ryushi A.

Hello Ryushi,

If you want to reset CMPSS on edge changes you could do following steps:

1. Enable CMPSS Ramp generator

2. Generate Sync event from EPWM: Configure SOCA event to happen on PWMA rising edge, i.e CTRU = CMPA 

3. Route SOCA to CMPSS via TRIPSEL

4. Enable CMPSS Ramp sync with PWM event: select corrent sync source from PWMxSOCA

ryushi asami said:

CMPSS or CMPx(as time limit) make PWMA low, and CMPSS or period(as time limit) make PWMA high.

Addition to Stevan comments:

Set PWM edge events sync CMPSS blanking with added offset into PWM periods of DAC filter pulse detection. Blanking counter measures CMPSS ramp generator CBC pulses advised TRM pages when DACVAL-H/L cause missing edge events into next PWM period. Likely the TRM advisory notes from missing CMPSS over current edge events high voltage DC current monitoring on primary T1 of DC/DC converters etc...

Seemingly CMPSS blanking of ramp generator output can offset odd CBC minor over current spikes causing random fault events we like to ignore.

We separate CMPSS DAC-H/L Filter events from the ORD async path as a rule. Then DAC filter Alone sets CBC events direct into ePWM xBAR MUX. C2000ware OR's direct async path with DAC filter, like heart bypass stint. Easy fix, modify C2000Ware calls ~OR the Async path with DAC filter, set blanking offsets in PWM period and CMPSS configurations. 

Hello Stevan,

>3. Route SOCA to CMPSS via TRIPSEL

Please explain this routing.

Our recognisation, SOC is Start Of Conversion of ADC.

TRIPSEL can select ADCxEVTy.

How can we connnect SOC to ADCxEVT?

And, please continue to investigate the following questions.

>Q:Can ePWM modules sync itself?

Best regards.

Ryushi.A

ryushi asami said:

>Q:Can ePWM modules sync itself?

Not exactly as you have to set conditions in software for generators to sync up by PRD clock. Most PWM modules can assert driverlib commands for assigning Master generator to slave generators modes. There is example PWM projects can download using CCS and REX to review prior to accepting import into CCS project tree.  

ryushi asami said:

Our recognisation, SOC is Start Of Conversion of ADC.

Correct and again review example PWM projects will get you way ahead in understanding those connections. The TRM tends to break the modules into sections for individual circuit analysis. Seeing example PWM SOC code will greatly aid your questions. There are several parts to make PWM SOC trigger ADC sample conversions interrupts. Though you have to setup the CMPSS inputs/outputs and PWM action qualifiers to handle ePWM xBAR MUX trip zones and produce sync pulses to CMPSS to clear the DAC latches CBC.  Can set PWM action qualifier (xBAR MUX trip zones DACL/H EVENT2 for CBC trips originating from CMPSS ramp generator. Note it's very complex routing in software not for the beginner.  TI offers TIDI DC/DC converter code project and evaluation PCB for certian LaunchXL, may save you some time experimenting. The TIDI experimental kit is highly advised to purchase in researching complex DC/DC converters. 

Hello Genatco,

We understand that connecting SOC to ADCxEVT as below:

1.Setting SOCn of ADCx

2.Seting ADCxPPBm that triggered by SOCn

3.Input them by XBAR

But we don't have spare ADCs, so the SOC may not start immediately by conflicting other SOCs.

Is it correct?

Best regards.

Hi Ryushi,

We don't use sys config for firmware development. However, consult the TRM tables for ADC, xBAR MUX and other connections. There is a complete DC/DC converter example project to download via CCS tool bar REX, some examples have sys config project too.

Regards,